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ESP32-S31 Hardware Design Guide: Power, Boot, USB, Ethernet, and RF

Quick Answer

SpeedUp turns product requirements for an ESP32-S3 board into an electronics architecture for power, boot configuration, USB, memory, programming, and peripheral interfaces, structured schematic sheets, and an editable KiCad project for engineering review. Explore the SpeedUp Demo: ESP32 E-Ink MQTT Display to see this handoff in a real project.

An ESP32-S31 schematic should be reviewed as a complete system, not as a copied MCU symbol. First decide whether the design uses an ESP32-S31 module or the bare SoC. Then verify every supply pin and local capacitor, CHIP_PU timing, boot-strapping states, external flash, the compulsory 40 MHz crystal, USB interfaces, Ethernet PHY connections, RF matching, and the final pin budget.

For a bare-chip design, Espressif currently recommends a 3.3 V supply capable of at least 800 mA, a defined CHIP_PU network, off-package NOR flash, and a 50 Ω RF path. The exact capacitor, inductor, matching, and pin choices depend on the package and PCB. If schedule and RF risk matter more than maximum integration, an ESP32-S31-WROOM module is usually the safer starting point.

Documentation status: Espressif announced ESP32-S31 mass production in July 2026, but the public data sheet available during this review is marked preliminary. Recheck the latest silicon revision, data sheet, hardware-design guidelines, module documentation, errata, and ESP-IDF support before freezing a production design.

What ESP32-S31 Adds

ESP32-S31 is Espressif’s high-performance connectivity SoC built around dual 32-bit RISC-V cores running at up to 320 MHz, with a low-power coprocessor, 512 KB of SRAM, and support for external high-speed PSRAM. Its integrated wireless set includes 2.4 GHz Wi-Fi 6, Bluetooth 5.4 LE and Classic, plus IEEE 802.15.4 for Zigbee and Thread. It also adds a Gigabit Ethernet MAC and high-speed USB capabilities. See the official ESP32-S31 product page and mass-production announcement for the current product summary.

Those features make the schematic more capable, but not automatically simpler. USB and Ethernet consume pins and add signal-integrity constraints. Multi-radio products need antenna, enclosure, coexistence, and certification planning. External memory adds another fast interface. The right first schematic is therefore a constrained architecture, not a symbol with every peripheral broken out.

First Decision: Module or Bare ESP32-S31?

Decision area	ESP32-S31-WROOM module	Bare ESP32-S31 SoC
RF design	Module integrates the chip, crystal, memory, and RF implementation. Follow the module antenna keepout and placement rules.	You own the 50 Ω path, matching network, antenna or connector, layout tuning, and RF validation.
Memory and clock	Integrated according to the selected module variant.	External flash and the compulsory 40 MHz crystal must be designed and routed correctly.
PCB area and BOM	Larger module footprint, fewer RF and memory parts to source and validate.	Potentially smaller or more integrated product, with higher engineering and validation effort.
Best fit	Prototypes, lower-to-medium volumes, compressed schedules, and teams reducing RF risk.	High-volume or space-constrained products with experienced RF, layout, test, and compliance resources.

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Do not mix the two reference approaches. Module matching values and layout decisions are not a drop-in bare-chip RF design. Start from the documentation for the exact orderable part, including the ESP32-S31-WROOM-3 data sheet when using that module.

ESP32-S31 Schematic Review Checklist

Block	Minimum review	Common failure
Power	3.3 V current margin, all rail pins, local capacitors, RF rail filtering, startup behavior	Brownout or radio resets caused by supply droop and distant bypass parts
Reset	CHIP_PU never floating, correct RC or supervisor, rails stable before release	Intermittent boot during slow or noisy power ramps
Boot and programming	GPIO37/60/61 straps, download mode access, UART0 or USB debug path	External loads force the wrong boot mode
Memory	Validated NOR flash, supported mode, rail voltage, optional series footprints, short routing	Unqualified flash or copied high-speed routing fails across temperature
Clock	40 MHz crystal, load-cap calculation, required series inductor, optional 32.768 kHz path	Crystal starts in the lab but misses frequency or startup margin
USB	Choose HS OTG versus Serial/JTAG, connector CC network, ESD, controlled routing, VBUS behavior	USB-C power works but data or programming does not
Ethernet	External PHY, interface mode, reference clock direction, strap states, magnetics and ESD	Treating the internal MAC as a complete Ethernet port
RF	50 Ω trace, matching footprints, antenna keepout, enclosure and tuning plan	Copying another board’s matching values without tuning this PCB
GPIO plan	Package pinout, straps, dedicated interfaces, voltage domains, startup states, test access	Discovering after layout that two required functions need the same pin

Use this as a review index, then check the current Espressif ESP32-S31 schematic checklist and ESP32-S31 data sheet for exact limits and package pin assignments.

Power Supply and Decoupling

Espressif recommends a single 3.3 V supply with at least 800 mA available for a bare ESP32-S31 design. That rating is a starting point for the SoC, not a complete product power budget. Add display, Ethernet PHY, sensors, USB peripherals, external memory, LEDs, relays, and peak radio activity before selecting the regulator. Review input-source tolerance, thermal dissipation, startup ramp, transient response, brownout behavior, and the real battery or USB current limit.

Each supply group needs the capacitors shown in the current hardware guide placed close to its pins with a short return path. The main power entry should include ESD protection and at least 10 µF of bulk capacitance. VDDPST_1 uses local 0.1 µF and 1 µF bypassing; the analog and RF supply groups have their own local networks. Espressif highlights VDDA3 and VDDA4 because RF bursts create fast current demand, and recommends an LC-filtered path with an inductor rated for at least 500 mA.

Treat those values as net-specific requirements, not one generic “decoupling bank.” Verify the exact pins and latest values for the selected package, then apply the decoupling capacitor value and PCB placement checklist before layout.

CHIP_PU, Reset, and Boot-Strapping Pins

CHIP_PU enables the chip when HIGH and resets it when LOW. It must never float. The supply rails need to be stable before CHIP_PU rises; the current Espressif guide specifies at least 1 ms for both power stabilization and reset-low time. A 10 kΩ pull-up with 1 µF to ground is the initial RC recommendation. When the source ramps slowly, dips during startup, or can cycle unpredictably, reserve a reset supervisor with an appropriate threshold instead of expecting one RC pair to fix every waveform.

GPIO37, GPIO60, and GPIO61 are strapping pins. GPIO60 and GPIO61 participate in boot-mode selection; the normal SPI boot condition and download-mode condition must match the latest table. Espressif recommends a pull-up on GPIO61 and warns against a high-value capacitor there. Audit every peripheral, level shifter, connector, and test jig attached to a strap pin. A device that is high impedance after boot can still force the wrong level during reset.

Also make programming and recovery deliberate. UART0 uses GPIO58 and GPIO59 by default for downloads and logs, with a 499 Ω series resistor recommended on U0TXD. If the product relies on USB Serial/JTAG instead, retain accessible pads or a connector strategy that works when the main application firmware is broken.

Flash, PSRAM, and Clock Design

A bare ESP32-S31 requires off-package NOR flash for the current firmware flow. Confirm the supported interface mode, flash voltage, capacity, package, temperature grade, and exact part against the current qualified list. Espressif’s guidance allows SPI, dual, and quad modes and describes capacities up to 256 MB. Reserve zero-ohm series-resistor footprints on fast flash signals so bring-up can tune edges without cutting traces.

Some variants integrate octal 1.8 V PSRAM inside the package; those internal PSRAM pins are not bonded out for reuse. For any external high-speed memory, follow the package-specific pin and routing guidance and validate the supported ESP-IDF configuration before committing the BOM.

The 40 MHz crystal is compulsory for the bare-chip design and should meet the current ±10 ppm accuracy requirement. The published checklist calls for a 24 nH, 0201 series inductor on XTAL_P even when RF is not used. Calculate the initial load capacitors from the crystal load specification and measured stray capacitance, then verify startup and frequency on the assembled PCB. If the optional 32.768 kHz crystal is used, check its ESR and reserve the bias-resistor footprint described by Espressif.

USB-C, High-Speed USB, and Serial/JTAG

ESP32-S31 exposes separate high-speed USB OTG and USB Serial/JTAG paths. Decide which interface powers the board, programs it, carries product data, or supports host/device operation. Then trace each connector pin to the intended controller pins; a board can enumerate on one interface while the recovery workflow expects the other.

For USB Serial/JTAG, Espressif recommends reserving 22 Ω or 33 Ω series resistors and optional shunt-capacitor footprints close to the chip for signal tuning. The complete USB-C design also needs correct CC resistors for the chosen power role, ESD protection with a short return, VBUS sensing and power-path behavior, controlled differential routing, connector orientation, shield treatment, and no accidental back-power path. Use the USB-C schematic checklist before PCB layout for that connector-level review.

Gigabit Ethernet MAC and External PHY

The ESP32-S31 includes an Ethernet MAC, not the analog PHY, magnetics, connector, protection, and termination required for a physical network port. Select a supported external PHY and one interface mode—MII, RMII, or RGMII—then confirm pin availability, IO voltage, clock direction, reset timing, strap resistors, MDIO/MDC management, and the PHY’s own power rails.

Clock topology deserves an explicit diagram. The hardware guide recommends a series footprint on the clock signal for tuning. In RMII, GPIO13 is a clock input; designs needing an output clock use the specified alternative clock pad and connection scheme. Do not infer direction from a signal name. Follow the exact current table for the selected interface and route the high-speed group according to both SoC and PHY requirements.

At the connector side, review magnetics, chassis and digital ground strategy, common-mode protection, ESD discharge path, center-tap power, PoE requirements if any, and differential-pair constraints. Ethernet is a subsystem, not one MAC-to-RJ45 net bundle.

RF Matching, Antenna, and PCB Layout

For the bare SoC, route the RF signal as a controlled 50 Ω transmission line. Place the matching network immediately next to the chip, preserve at least two configurable CLC sections, and use the component size recommended in the current guideline. Espressif suggests a CLCCL arrangement near the SoC and another CLC section near the antenna. Initial values are not final values: stackup, ground shape, enclosure, battery, display, cable, antenna, and assembly tolerances all change the measured impedance.

Do not copy module matching values onto a custom bare-chip board. Reserve tuning footprints, control the ground and keepout geometry, prevent digital traces from crossing the RF return path, and plan conducted and radiated test access. A module can reduce this risk, but the carrier PCB still has to respect its antenna keepout, edge placement, ground clearance, enclosure materials, and certification conditions.

GPIO and Peripheral Pin Planning

ESP32-S31 offers up to 60 GPIOs, but “up to” is not the number freely available to your design. Package selection, boot straps, UART0, memory, USB, Ethernet mode, crystal pins, RF, power domains, debug access, touch or display functions, and internal package options all reduce or constrain the usable set.

Lock the exact package or module variant and import the matching official pin table.
Allocate non-negotiable functions first: supplies, grounds, RF, clocks, memory, straps, reset, programming, USB, and Ethernet.
Record every pin’s reset state, pull state, voltage domain, and board-level load.
Assign flexible buses and GPIO only after the fixed functions are conflict-free.
Reserve test access for power rails, reset, boot, debug, USB, Ethernet clocks, and RF where appropriate.
Run a final pin audit against the latest data sheet and selected ESP-IDF peripheral configuration.

A Real SpeedUp Example: System-Level ESP32 Review

The existing ESP32 E-Ink MQTT display schematic example uses an earlier ESP32 family device, not ESP32-S31, so it is not a pin-compatible reference design. It is useful here for a different reason: the generated project separates power, MCU, display, buttons, LEDs, and connectors into reviewable sheets instead of hiding the product behind one block.

SpeedUp-generated ESP32 MCU schematic sheet used as a system-level review example. — This real SpeedUp-generated ESP32 MCU sheet is evidence of the review workflow, not an ESP32-S31 reference schematic. An S31 version must replace the symbol, pinout, power networks, memory, clocks, boot circuitry, and RF implementation using current official documentation.

For an ESP32-S31 product, that same decomposition should expose the additional high-risk blocks: every supply group, CHIP_PU and straps, flash and PSRAM, 40 MHz clock, the selected USB paths, external Ethernet PHY, RF section, and a pin-allocation table. The structure makes review faster; it does not eliminate engineering verification.

ESP32-S31 vs ESP32-S3 for New Designs

ESP32-S31 is not simply a faster ESP32-S3. According to Espressif’s official ESP32-S31 FAQ, S31 moves to dual RISC-V application cores up to 320 MHz and adds Wi-Fi 6, IEEE 802.15.4 for Zigbee and Thread, Bluetooth Classic alongside BLE, Gigabit Ethernet MAC, high-speed USB, and new accelerators. These additions can consolidate a connected product that would otherwise need more companion ICs.

Choose S31 when its connectivity, compute, memory, or interface set materially improves the product architecture and the newer platform fits your software and supply plan. Choose S3 when its mature ecosystem, existing firmware, qualified modules, known RF path, and adequate performance reduce schedule and lifecycle risk. The schematic decision should include SDK readiness, module availability, certifications, power, package, memory, board complexity, and the team’s ability to validate a new platform—not just headline clock rate.

Common ESP32-S31 Hardware Design Mistakes

Using a generic ESP32 symbol or an ESP32-S3 reference design as if the ESP32-S31 pinout and power network were interchangeable.
Selecting the package after GPIO assignment, then discovering conflicts with fixed interfaces and strapping pins.
Sizing the regulator for average current while ignoring radio, USB, Ethernet, display, and external-memory transients.
Letting CHIP_PU float or relying on an RC reset network without checking the actual supply ramp.
Attaching LEDs, level shifters, or peripherals to boot straps without analyzing their reset-time state.
Choosing flash or PSRAM by capacity alone without validating interface, voltage, timing, and software support.
Treating USB-C, Ethernet, or RF as schematic-only interfaces and postponing return-path and impedance decisions until layout.
Copying RF matching values from a development board or module onto a different stackup and antenna geometry.
Freezing the design against a preliminary document without a revision and errata check.

What SpeedUp Generates Before Engineering Review

SpeedUp can turn an ESP32-S31 product requirement into a structured KiCad schematic draft with explicit power, reset, boot, memory, USB, Ethernet, RF, connector, and test-point sheets. That gives an engineer a concrete design to review against the official data sheet instead of starting from an empty canvas or an unrelated reference board.

The generated schematic is an engineering draft, not a production-ready Espressif reference design. The engineer still selects the exact orderable part, replaces provisional symbols or footprints, validates every limit and approved component, completes PCB stackup and high-speed/RF layout, tests hardware, qualifies sourcing, and finishes safety, EMC, radio, and manufacturing compliance. The AI-generated KiCad schematic review guide provides the broader review workflow.

Product boundary: For an ESP32-S31 product, SpeedUp can turn power, reset, boot, memory, USB, Ethernet, RF, connector, and test requirements into electronics architecture, structured sheets, and an editable KiCad first draft. It does not replace the current Espressif documentation, approve provisional libraries, complete high-speed or RF layout, develop firmware, test hardware, qualify sourcing, or provide compliance and manufacturing sign-off. See the SpeedUp AI schematic generator workflow for the complete product-brief-to-editable-project path.

Related SpeedUp Guides

KiCad schematic checklist before PCB layout — validate constraints, footprints, return paths, placement, and fabrication readiness after the circuit review.
Use the official ESP32-S31 ESP-IDF getting-started guide to confirm the current toolchain, target support, programming flow, and example projects.
Review the official ESP32-S31 Function CoreBoard user guide for a module-based evaluation platform and bring-up reference.

FAQ

What power supply does ESP32-S31 need?

For a bare SoC, Espressif currently recommends a 3.3 V supply with at least 800 mA available. The final regulator must also support all other loads and real transient, thermal, startup, and source conditions. A module design must follow the exact module data sheet.

Does ESP32-S31 need external flash?

A bare ESP32-S31 uses off-package NOR flash for the current firmware flow. Some module or package variants integrate memory, so check the exact orderable part. Validate the flash model, voltage, interface mode, capacity, routing, and current ESP-IDF support.

Does ESP32-S31 have Ethernet?

It includes a Gigabit Ethernet MAC. A physical Ethernet port still needs an external PHY plus its power, reference clock, straps, management interface, magnetics, connector, protection, and PCB layout.

Does ESP32-S31 support Zigbee and Thread?

Yes. ESP32-S31 integrates IEEE 802.15.4 alongside 2.4 GHz Wi-Fi 6 and Bluetooth 5.4, enabling Zigbee, Thread, and Matter-related architectures subject to the current software stack and certification requirements.

Can I copy an ESP32-S3 schematic for ESP32-S31?

No. It can help identify product-level blocks, but the pinout, power groups, boot straps, memory, clocks, USB, Ethernet, RF network, package, and software target must be rebuilt or verified from the ESP32-S31 documentation.

Should I use an ESP32-S31 module or the bare chip?

Use a module when schedule, RF risk, lower engineering effort, and easier prototyping dominate. Consider the bare chip when volume, PCB area, integration, or custom antenna requirements justify the added memory, clock, RF, layout, test, sourcing, and certification work.

Is the ESP32-S31 data sheet final?

The public data sheet reviewed for this article is marked preliminary even though Espressif has announced mass production. Check the current revision, errata, hardware guidelines, module documentation, and ESP-IDF release notes immediately before design freeze.

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July 30, 2026

LED Current-Limiting Resistor: Formula, Values, and Power Rating

Quick Answer

SpeedUp connects product requirements for LED indicators to an electronics architecture centered on supply voltage, target current, resistor values, and component placement, then carries the design into structured schematic sheets and an editable KiCad project for engineering review. See the SpeedUp Demo: ESP32 E-Ink MQTT Display for a live example of the prompt-to-project handoff.

For one indicator LED in a simple series circuit, calculate the current-limiting resistor with R = (VDRIVE − VF − VSWITCH) / ILED. Use the supply or loaded GPIO output voltage for VDRIVE, the LED forward voltage at the intended current for VF, and any transistor or GPIO output drop for VSWITCH. Select a nearby standard resistor value—usually rounding upward when protecting the LED is the priority—then verify brightness, resistor power, GPIO current, voltage tolerance, LED temperature, and worst-case component variation.

A resistor limits current; it does not create an accurate constant-current source. It is a good fit for many low-power indicator LEDs on a reasonably stable rail. Use a dedicated LED driver or constant-current circuit when supply range, LED power, brightness matching, efficiency, thermal behavior, or series-string voltage makes the resistor solution unreliable.

Why an LED Needs Current Limiting

An LED is not a fixed resistance. Once its forward voltage is reached, a small voltage increase can produce a large current increase. Connecting an ordinary indicator LED directly across a low-impedance supply can exceed the LED, GPIO, transistor, or connector rating. The result may be immediate failure, gradual loss of brightness, a stressed microcontroller pin, or a circuit whose current changes sharply with temperature and part variation.

The series resistor takes the voltage that is not dropped by the LED and converts it into a controlled current according to Ohm’s law. Analog Devices’ guide to driving LEDs from push-pull outputs expresses the same design relationship while including the output-pin voltage drop. That extra term matters: a loaded GPIO high is not always equal to its supply, and a loaded GPIO low is not always exactly ground.

Current limiting belongs in a complete schematic review checklist because the resistor value affects several blocks at once: LED brightness, MCU pin current, battery life, thermal margin, PWM behavior, and whether the user can see the indicator in the real enclosure.

LED Current-Limiting Resistor Formula

For an LED and resistor connected in series to a voltage source:

R = (VSUPPLY − VF) / ILED

When a GPIO or transistor drives the LED, use the voltage available across the resistor rather than the ideal rail voltage.

GPIO sourcing current: R = (VOH − VF) / ILED
GPIO sinking current: R = (VSUPPLY − VF − VOL) / ILED
Low-side transistor or MOSFET: subtract the transistor’s on-state drop at the intended current.

Use amperes in the equation. For example, 5 mA is 0.005 A. The calculated result is the theoretical resistance for the chosen input values; it is not automatically the correct production part.

Worked example: 3.3 V red indicator LED

Assume a 3.3 V source, an LED forward voltage of 1.9 V at the intended operating point, and a target current of 5 mA:

R = (3.3 V − 1.9 V) / 0.005 A = 280 Ω

A designer might select 300 Ω or 330 Ω, depending on the available resistor series, desired brightness, and worst-case analysis. With 330 Ω and the same assumed voltages, the nominal current is about 4.2 mA. If a GPIO drives the LED, repeat the calculation with the guaranteed loaded VOH or VOL, not 3.3 V or 0 V by assumption.

Choose a Standard Value and Check Both Current Corners

The calculated resistance may not be a stocked E-series value. Rounding upward reduces current for the nominal assumptions, which is often a sensible first choice for an indicator. It is not the end of the design. A larger resistor may make the LED too dim at low supply voltage, high forward voltage, cold temperature, or a loaded GPIO output. Choose one or more candidate values, then calculate both the maximum-current and minimum-current corners.

For an ideal voltage source, the bounding equations are:

IMAX = (VDRIVE,MAX − VF,MIN − VSWITCH,MIN) / RMIN
IMIN = (VDRIVE,MIN − VF,MAX − VSWITCH,MAX) / RMAX

As an illustration, assume a nominal 3.3 V source with ±5% tolerance, an LED forward-voltage range of 1.7 V to 2.1 V at the relevant current and temperature, and a 330 Ω resistor with ±5% tolerance. Ignoring driver drop only for this example, the high-current corner is approximately (3.465 − 1.7) / 313.5 = 5.6 mA. The low-current corner is approximately (3.135 − 2.1) / 346.5 = 3.0 mA. Both results differ materially from the 4.2 mA nominal calculation.

For a real GPIO, replace the ideal source with the manufacturer’s guaranteed output specification at the selected drive strength. Also check whether several LEDs can switch on together. Per-pin current may pass while the total current for one port, supply domain, or device exceeds its allowed operating condition.

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Illustrative LED Resistor Table

The following table behaves like a compact calculator example for a 3.3 V ideal source and 5 mA target. The forward-voltage values are assumptions, not universal values for each color. Replace them with the selected LED’s datasheet values and include the real driver voltage drop.

Illustrative LED	Assumed VF	Calculated R at 5 mA	Example rounded value	Approx. current
Red indicator	1.8 V	300 Ω	330 Ω	4.5 mA
Green/amber example	2.1 V	240 Ω	270 Ω	4.4 mA
Blue/white example	2.9 V	80 Ω	100 Ω	4.0 mA

The blue/white example has little voltage headroom. A lower supply, higher LED forward voltage, or loaded GPIO output can reduce the current sharply or prevent reliable illumination. That is a reason to review the complete circuit rather than selecting a resistor from LED color alone.

LED Resistor Design Checklist

Review item	What to verify	Why it matters
LED data	Part number, color, forward-voltage range at current, recommended current, absolute maximum, and temperature behavior.	Color and package do not define one fixed forward voltage.
Drive voltage	Supply tolerance or guaranteed GPIO `VOH`/`VOL` at the intended drive mode and current.	The output pin is not an ideal voltage source.
Target current	Choose the current needed for visible brightness in the enclosure, not automatically the LED maximum.	Modern indicator LEDs can be bright well below 20 mA.
Worst-case current	Check maximum drive voltage, minimum LED forward voltage, minimum resistor tolerance, and lowest switch drop.	Nominal current may hide the highest electrical stress.
Minimum brightness	Check minimum drive voltage, maximum LED forward voltage, maximum resistor tolerance, and temperature.	A protected LED can still be too dim or fail to turn on reliably.
GPIO budget	Per-pin source/sink current, output-voltage guarantees, configured drive strength, and total port/device limits.	Several safe individual LEDs can exceed the combined MCU current budget.
Power rating	Calculate resistor dissipation and apply thermal, ambient, pulse, and derating margin.	Higher supply voltage can make resistor heating the real constraint.
PWM and states	Peak current, duty cycle, reset state, boot behavior, active-high/low polarity, and sleep leakage.	PWM changes average brightness but does not remove the peak-current requirement.

How to Calculate the Resistor Power Rating

Calculate the resistor’s dissipation with either:

P = I²R
P = VRESISTOR × I
P = VRESISTOR² / R

In the 3.3 V, 1.9 V, 330 Ω example, the resistor drops about 1.4 V at 4.2 mA and dissipates roughly 6 mW. That is small for many SMD resistors, but do not generalize from a low-voltage indicator. A 24 V control panel, an automotive LED, or several LEDs can dissipate far more power. Check the resistor manufacturer’s rating at the real ambient temperature, PCB copper, package size, pulse pattern, and enclosure conditions; do not operate continuously at the headline power rating without appropriate margin.

GPIO Source, Sink, and PWM Checks

A microcontroller pin may source current into a resistor and LED to ground, or sink current from a supply-connected LED. Both can work, but the equations and active polarity differ. Sinking often gives a different current capability and makes the LED active-low; sourcing makes it active-high. Firmware, boot configuration, and reset defaults must match the schematic.

For an nRF52840 example, the Nordic GPIO electrical specification lists different guaranteed output levels and currents for standard and high-drive modes. A resistor calculation should use those loaded output specifications and check the selected drive configuration. The absolute maximum rating is not a recommended continuous operating point.

PWM controls average LED brightness by switching the current on and off. The series resistor must still limit the instantaneous on-current. Verify the peak current, duty cycle, PWM frequency, GPIO transition behavior, LED pulse rating, visible flicker, camera interaction, and power consumption. Do not multiply the resistor value by duty cycle as though the LED receives a smaller peak voltage.

One Resistor Per LED and Other Topology Rules

LEDs connected in series share the same current, so one resistor can limit the string if the supply provides enough headroom for the sum of forward voltages plus driver drop. LEDs connected in parallel should normally have individual resistors or controlled current paths. Small forward-voltage differences can make one parallel LED take more current and heat up, which can further change current sharing.

The resistor may be placed on the anode side or cathode side of one series LED; the same current flows through both parts. PCB placement is usually not as high-frequency-critical as a decoupling capacitor, but the schematic should keep the resistor clearly associated with its LED and control signal. Check LED polarity, connector orientation, test access, silkscreen, optical location, and whether the indicator will be blocked by the enclosure. The KiCad schematic-to-layout checklist covers those handoff questions.

Example From a Real SpeedUp Project

SpeedUp-generated engineering evidence: KiCad user interface schematic with two 680 ohm current-limiting resistors driving record and status LEDs. — The real SpeedUp-generated AI recorder project exposes separate 680 Ω resistors for record and status LEDs, making the values and control nets reviewable before layout.

The magnetic AI microphone / AI recorder KiCad project includes two indicator paths. UI_RECORD_LED_EN drives LED D5 through R23 = 680 Ω, while UI_STATUS_LED_PWM drives D6 through R24 = 680 Ω. Separate resistors are the right structural pattern because each LED has its own control signal and current path.

The screenshot does not prove that 680 Ω is the final production value. The generated symbol records part names for a red and yellow LED, but the KiCad datasheet fields are empty. A reviewer must still obtain the real LED forward-voltage curves, confirm the nRF52840 supply and GPIO drive mode, calculate high- and low-current corners, check brightness through the product enclosure, and verify resistor footprints and power. This is exactly the difference between a useful schematic draft and a validated circuit.

Verify the LED Current on the Bench

Measure the voltage across the series resistor while the LED is on, then calculate current with I = VRESISTOR / R. This avoids adding an ammeter in series and disturbing a small circuit. Use a meter or oscilloscope with suitable input impedance and bandwidth, and confirm the actual resistor value when accuracy matters.

For PWM, observe the resistor voltage during the on pulse as well as its average. The peak waveform confirms whether the resistor limits current as intended; the duty cycle determines average current and brightness. Check startup, reset, firmware update, sleep, and fault states because the LED may turn on continuously before PWM begins or while a pin is still in its default configuration.

Test at minimum and maximum supply voltage, across representative temperature, and with the real diffuser, light pipe, window, or enclosure. Human-visible brightness does not scale linearly with current, and two LEDs with the same calculated current can look different because of color, viewing angle, optical efficiency, and binning. Record the chosen current and acceptance criteria so a later LED substitution does not silently invalidate the resistor value.

When a Series Resistor Is Not Enough

Use a current-regulated driver rather than a simple resistor when the LED is high power, the supply varies widely, several series LEDs approach the supply voltage, brightness matching matters, thermal changes are large, or efficiency is important. Battery systems can be especially awkward: LED current may change from a fully charged cell to the end-of-discharge voltage, and a blue or white LED can lose headroom before the rest of the system stops working.

A constant-current sink, linear LED driver, or switching LED driver regulates current more accurately. It adds component, thermal, layout, and sometimes EMI requirements, so choose it for a defined reason. For a low-current status LED, a resistor is often simpler and entirely adequate after worst-case review.

Common LED Resistor Mistakes

Using 220 Ω by habit: the correct value depends on supply, LED forward voltage, current, and driver drop.
Calculating from the LED maximum current: an indicator may meet brightness requirements at a much lower, safer current.
Ignoring GPIO output droop: the pin’s guaranteed VOH/VOL changes with current and drive mode.
Checking only nominal values: supply, forward voltage, resistance, temperature, and tolerance move the current.
Sharing one resistor across parallel LEDs: current may not divide predictably.
Applying PWM without peak-current analysis: duty cycle reduces average light but does not automatically protect the on-state path.
Forgetting resistor power: a higher-voltage system can overheat a small resistor even at modest LED current.
Leaving the LED datasheet blank: color and footprint are not enough to validate forward voltage, current, polarity, and luminous output.

How SpeedUp Fits

SpeedUp can turn a product prompt into an editable KiCad draft that shows indicator LEDs, series resistors, GPIO control nets, power domains, and intended functions. That makes missing resistors, shared current paths, active-low behavior, and unresolved part data visible early. The goal is not to claim that one generated resistor value is automatically correct; the goal is to give an engineer a structured circuit they can calculate, inspect, and revise.

Engineers still verify the LED and MCU datasheets, electrical corners, power, brightness, PCB placement, firmware states, sourcing, thermal behavior, EMC, manufacturing, and enclosure optics. Related component-review guides include the decoupling capacitor value and placement guide and the flyback diode polarity and sizing guide.

FAQ

What resistor should I use for an LED?

Calculate R = (VDRIVE − VF − VSWITCH) / ILED, then select a standard value after checking maximum current, minimum brightness, GPIO limits, resistor power, and tolerances. There is no universal resistor for every LED.

Why is 220 Ω often used with LEDs?

It is a convenient common value that produces a visible current in some 3.3 V or 5 V beginner circuits. It may be too low, too high, or impossible to use in another circuit. Calculate from the actual voltage, LED, target current, and output driver.

Can the resistor go before or after the LED?

Yes. In one simple series branch, the same current flows through the resistor and LED, so the resistor can be on the anode or cathode side. Keep the schematic clear and preserve the intended active-high or active-low drive topology.

Do I need a resistor when using PWM?

Usually yes for a basic voltage-driven indicator LED. PWM controls average brightness, while the resistor or current driver limits the instantaneous current during each on pulse.

Can multiple LEDs share one resistor?

Series LEDs can share one resistor because they carry the same current, provided the supply has enough voltage headroom. Parallel LEDs should normally have individual resistors or regulated current paths because their forward voltages and current sharing differ.

Should I use a resistor or a constant-current LED driver?

Use a resistor for many low-current indicators on a stable rail. Consider a constant-current driver for high-power LEDs, wide supply ranges, series strings, matched brightness, better efficiency, or applications where LED current must remain controlled across temperature and battery voltage.

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July 27, 2026

Decoupling Capacitor: Values, Placement, and PCB Layout Checklist

Quick Answer

SpeedUp uses product requirements for stable IC power rails to shape an electronics architecture around local bypassing, bulk capacitance, return paths, and placement constraints, then generates structured schematic sheets and an editable KiCad project for engineering review. See the SpeedUp Demo: XC7Z010 Discrete Power System for a live example of the prompt-to-project handoff.

A decoupling capacitor supplies short bursts of current near an IC and gives high-frequency noise a low-impedance path away from the power pin. Start with the component datasheet or reference design; a 100 nF ceramic capacitor at each relevant supply pin is a common pattern, not a universal rule. Add the local and bulk capacitance required for the device, rail, regulator, and load-transient conditions, then place the high-frequency capacitor close to the pin with a short power-and-ground loop.

The schematic must show the correct values and rail assignments, but PCB placement determines whether those capacitors work at high frequency. A capacitor drawn beside an IC can still be ineffective if layout adds a long trace, shared via, narrow return path, or large loop area. Review the schematic, datasheet, package, and PCB together before treating the power network as complete.

What a Decoupling Capacitor Actually Does

Digital gates, radios, converters, displays, sensors, and analog circuits do not draw perfectly steady current. Their demand changes with clock edges, switching states, transmissions, conversions, and load steps. The upstream regulator and board-level power plane cannot respond to every fast event without some voltage movement because traces, planes, packages, and vias all have resistance and inductance.

A local capacitor stores charge near the load. During a fast current step, it helps hold the supply voltage while current from the wider power network catches up. It also lowers the local power-distribution-network impedance over part of the frequency range. Analog Devices’ MT-101 decoupling tutorial explains why real capacitors have equivalent series resistance, equivalent series inductance, and a self-resonant frequency; above resonance, adding nominal capacitance alone does not guarantee lower impedance.

This is why “put one capacitor somewhere on the 3.3 V rail” is not a complete design instruction. The useful question is: which current transient is being supported, at which pin, over which frequency range, through what physical loop?

Decoupling Capacitor vs. Bypass Capacitor

Engineers often use decoupling capacitor and bypass capacitor interchangeably. Both usually describe a capacitor from a supply rail to its return node, placed so high-frequency current circulates locally instead of through a larger shared path.

When a distinction is made, decoupling emphasizes isolating one circuit block from disturbances created by another, while bypass emphasizes giving AC noise a low-impedance path around the load or into the return plane. In practical schematic and PCB review, the naming difference is less important than the capacitor’s value, dielectric, voltage bias, package, location, and current loop.

Decoupling Capacitor Schematic and PCB Checklist

Review area	What to check	Common failure
Datasheet requirement	Record every required capacitor value, rail, pin group, dielectric, ESR condition, and placement note.	Copying a generic 100 nF rule and missing a device-specific DEC, VCAP, AVDD, or regulator capacitor.
One capacitor per pin or group	Determine whether supply pins may share a capacitor or need dedicated local parts.	One remote capacitor is assigned to several fast power pins without a verified reference layout.
Capacitance under bias	Check effective capacitance at DC voltage, temperature, tolerance, and aging—not only the printed value.	A small high-value MLCC loses much of its capacitance at operating voltage.
Package and dielectric	Choose a suitable ceramic dielectric and package with acceptable ESR, ESL, voltage rating, and reliability.	Treating all 100 nF or 10 µF capacitors as electrically equivalent.
Placement	Put the highest-frequency local capacitor close to its power pin and return connection.	The schematic looks correct, but layout places the capacitor behind a long neck or on the opposite side with distant vias.
Loop geometry	Minimize the pin–capacitor–return loop with short, wide connections and nearby vias or planes.	Sharing a long ground via path or routing a narrow trace around another component.
Bulk capacitance	Add rail-, connector-, regulator-, or load-level energy storage where slower transients require it.	Expecting one tiny local capacitor to support a radio burst, motor step, display load, or long cable.
Regulator stability	Keep regulator input/output capacitors separate from generic bypass assumptions and follow the stability requirements.	Substituting value or ESR without checking the regulator datasheet and layout.
Verification	Review the PCB, BOM, rail ripple, startup, resets, emissions, and worst-case load transients.	Assuming ERC or a clean bench startup proves the power network is robust.

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How to Choose Decoupling Capacitor Values

1. Follow the exact datasheet and reference circuit first

A 100 nF ceramic capacitor is a widely used starting point for digital supply pins, but it is not a replacement for device documentation. Some ICs require a particular capacitor on an internal regulator, charge pump, reference, core rail, or analog supply. A regulator may specify an output-capacitance range and ESR condition for stability. An RF SoC may give package-specific component values and layout files. Those requirements outrank a generic checklist.

For example, Nordic Semiconductor’s nRF52832 reference circuitry tells designers to use the recommended package reference circuit and place the VDD bypass network close to the IC. The exact values and connections vary with device configuration and package, which is why copying a superficially similar Nordic circuit is unsafe.

2. Separate high-frequency local capacitance from bulk energy storage

A small ceramic capacitor near an IC pin has low mounting inductance and supports fast edges. A larger capacitor supports slower load changes and rail droop, but a physically larger package or remote location can reduce its usefulness at high frequency. Many boards therefore use a combination such as a local 100 nF part plus 1 µF, 4.7 µF, 10 µF, or more at the device, rail, regulator, or connector level.

Do not turn that example into a fixed recipe. Use transient current, allowable ripple, regulator response, plane impedance, and component models to decide the network. If several values are used, check their combined impedance and damping; “more decades of capacitance” can create anti-resonance peaks instead of a perfectly flat low-impedance rail.

3. Check the effective capacitance of the real part

MLCC capacitance can change with DC bias, temperature, tolerance, aging, and package stress. A 10 µF capacitor in a small package may provide substantially less than 10 µF at its operating voltage. Review the manufacturer’s bias curve and choose voltage rating, dielectric, case size, and nominal capacitance with enough margin for the application.

4. Treat analog, RF, switching, and sensitive reference rails separately

An ADC reference, PLL supply, RF rail, switching-converter input, op-amp supply, and ordinary GPIO rail may need different values, filtering, grounding, or isolation. Ferrite beads and series resistors are not automatically beneficial; they create another impedance element and can introduce resonance or DC drop. Use them only when the device guidance or power-integrity analysis supports the network.

Placement and PCB Layout Matter More Than Schematic Proximity

A schematic does not encode physical distance. Drawing C1 directly beside U1 does not guarantee that the board places it beside the correct pin. During placement review, trace the complete transient-current loop: device power pin, capacitor power pad, capacitor ground pad, ground return, and back into the device.

Texas Instruments’ CC13xx/CC26xx hardware and PCB guidance recommends placing decoupling capacitors close to the pin, keeping the return short and direct, and using separate ground vias to reduce noise coupling. Microchip’s decoupling-capacitor guidance similarly emphasizes close placement, low-ESR ceramic parts, short traces, and routing power through the capacitor before the device where applicable.

Practical layout checks include:

Place the local capacitor on the same layer as the IC when package and reference-layout guidance allow it.
Keep power and ground connections short and wide; avoid a long narrow trace between the capacitor and pin.
Put ground and power vias close to capacitor pads when planes are used.
Avoid sharing one long via or necked connection among several high-frequency capacitors.
Keep the return path continuous; do not cross a plane split or force current around a gap.
Give the smallest, highest-frequency local capacitor placement priority when several values are specified.
Copy a validated reference layout when the vendor identifies a critical regulator, RF, or high-current loop.

These checks belong in a broader schematic-to-PCB layout review. Component values, reference designators, footprints, placement constraints, planes, vias, and measurement access all need to survive the handoff into board layout.

Example From a Real SpeedUp Project

The featured schematic at the top of this guide comes from SpeedUp’s temperature and humidity sensor KiCad project. The control/display sheet places three capacitors on the controller’s 3.3 V supply: one 0.1 µF part and two 1 µF parts. It also shows the ATTINY816, I²C pull-ups, OLED supply, and ground connections in one reviewable block.

That is useful schematic evidence: the local capacitors exist, have values, and connect to the intended rail. It is not yet proof of effective high-frequency decoupling. Before production, the PCB reviewer still needs to confirm which capacitor belongs to which power pin or load, physical distance, trace and via geometry, effective capacitance under bias, regulator requirements, OLED load steps, and the return path.

A second example: why the exact device matters

SpeedUp-generated engineering evidence: Generated target SoC schematic showing multiple 0.1 microfarad, 1 microfarad, and 4.7 microfarad supply capacitors around an nRF52832 surrogate device. — SpeedUp-generated project evidence: This generated development-board sheet makes multiple supply capacitors visible, but it uses an nRF52832 surrogate and must not be treated as an nRF54L15 reference circuit.

The published Nordic development-board concept contains a generated target sheet with several 0.1 µF capacitors plus 1 µF and 4.7 µF parts. The visible grouping makes power-pin review easier, but the sheet uses an nRF52832 surrogate because the exact nRF54L15 symbol was not available in that generation. The lesson is not to reuse those values for nRF54L15. The lesson is to expose every rail and capacitor, then replace proxies and validate the exact device, package, reference circuitry, and layout before production.

How to Verify Decoupling on a Real Board

Visual inspection is the first check. Confirm that every schematic capacitor exists in the BOM and layout, uses the intended footprint, connects to the correct rail, and sits beside the intended power pin or pin group. Inspect the entire return path in the PCB editor rather than judging placement from component distance alone. A capacitor can look close while a plane split, distant via, narrow neck, or indirect route makes its loop electrically long.

On the bench, reproduce the operating events most likely to disturb the rail: processor wake-up, radio transmit, display refresh, sensor conversion, USB connection, motor or relay switching, and maximum simultaneous load. Watch for brownout resets, corrupted communication, ADC shifts, clock instability, unexpected emissions, or faults that disappear when a probe or extra capacitor is attached.

Measure supply ripple and transients with an appropriate probe connection. A long oscilloscope ground lead forms a large loop and can display ringing that belongs to the probe rather than the board. Use a short ground spring, coaxial tip, or dedicated measurement connector where the bandwidth and voltage allow it. Probe at the IC supply and return pins when possible, then compare the regulator output and other rail locations. Set bandwidth limits deliberately and document the measurement setup so results are repeatable.

If the design is sensitive or high speed, review the power-distribution network with impedance models, vendor capacitor data, or simulation. Include package and mounting inductance instead of treating capacitors as ideal values. Validate worst-case voltage, temperature, component tolerance, regulator control-loop behavior, and population changes. A quick fix—adding another capacitor—may hide one symptom while creating startup inrush, regulator instability, or an anti-resonance peak elsewhere.

Finally, keep the verified placement constraints with the design. Add PCB notes, courtyard or rule areas, pin-specific capacitor labels, and review comments so later routing, variant creation, or component substitution does not undo the working current loop.

Common Decoupling Capacitor Mistakes

Using 100 nF everywhere without reading the datasheet: device-specific rails and internal regulators may need different values or connections.
Counting schematic capacitors instead of reviewing current loops: ten remote parts can be less effective than one correctly mounted local part at the frequency that matters.
Ignoring DC-bias derating: the nominal capacitance may not survive the real operating voltage.
Sharing vias and narrow traces: common impedance couples noise between devices and raises the high-frequency impedance.
Placing a via between the capacitor and power pin without analysis: the extra inductance can weaken the local path.
Combining regulator capacitors with generic bypass parts: regulator input/output networks may have stability, ripple-current, and ESR requirements.
Adding many values blindly: parallel capacitors can create anti-resonance peaks and do not replace PDN analysis for demanding designs.
Treating ERC as a power-integrity test: ERC checks connectivity rules, not transient impedance, ripple, emissions, or physical placement.

What SpeedUp Generates Before Engineering Review

SpeedUp can turn a product prompt into an editable KiCad schematic draft with named rails, IC power pins, local capacitors, bulk-capacitor blocks, and review notes. That structure helps an engineer see whether a capacitor is missing, attached to the wrong rail, assigned an unexplained value, or disconnected from the intended functional block.

The generated result remains a first engineering draft. Engineers still verify the exact datasheet, reference design, symbols, footprints, capacitor part numbers, effective capacitance, regulator stability, PCB placement, return paths, signal integrity, thermal behavior, EMC, sourcing, manufacturing, and compliance. Use the complete schematic review checklist to keep those checks connected to the rest of the design.

Product boundary: For a design with multiple ICs and rails, SpeedUp can organize power domains, local and bulk capacitors, component context, and named connections into structured schematic sheets and an editable KiCad first draft. It does not prove transient impedance, regulator stability, effective capacitance, placement, return paths, signal integrity, EMC, or thermal performance; engineers must validate those properties in the real design. See the SpeedUp AI schematic generator workflow for the complete product-brief-to-editable-project path.

FAQ

What is the purpose of a decoupling capacitor?

It supplies local transient current and lowers the supply impedance over part of the frequency range. This helps reduce voltage droop, noise coupling, false resets, jitter, analog error, and emissions caused by fast load-current changes.

Is 0.1 µF the standard decoupling capacitor value?

A 0.1 µF or 100 nF ceramic capacitor is common at digital IC power pins, but it is only a rule of thumb. Follow the device datasheet and reference layout, then account for package, dielectric, voltage bias, rail behavior, frequency, and the need for larger local or bulk capacitance.

Does every power pin need its own decoupling capacitor?

Many fast devices require one capacitor per power pin or per closely grouped pin set, but the correct answer is device- and package-specific. Do not merge capacitors just because the pins share a rail name; check the reference circuit and layout guidance.

How close should a decoupling capacitor be to an IC?

As close as required to minimize the high-frequency current loop, preferably following the vendor’s reference layout. There is no universal distance that fits every package and frequency. Connection geometry, vias, planes, and return-path continuity matter as much as the distance measured in millimeters.

Can one bulk capacitor replace several small bypass capacitors?

Usually not. A bulk capacitor may support slower rail transients, while small local capacitors provide lower mounting inductance near fast power pins. The final network should be based on the device requirements and power-distribution impedance, not nominal capacitance alone.

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July 27, 2026

Flyback Diode: Polarity, Placement, and Sizing Guide

Quick Answer

SpeedUp starts with a product brief for an inductive load, maps driver switching, flyback-diode polarity, current paths, stress, and placement into the electronics architecture, and delivers structured schematic sheets with an editable KiCad project for engineering review. The SpeedUp Demo: 100W Desktop Charging Station shows the same workflow with concrete engineering artifacts.

A flyback diode gives current from a DC inductive load—such as a relay coil, solenoid, or simple brushed-motor stage—a safe path when its switch turns off. For a low-side driver, connect the diode directly across the load with its cathode, usually the striped end, toward the positive supply and its anode toward the MOSFET or transistor. Choose it for the load current, reverse voltage, stored energy, switching rate, temperature, and required release time. Do not assume one diode across the load is correct for an AC coil, H-bridge, or three-phase BLDC inverter.

The diode is not there to carry normal load current. It is reverse-biased while the load is energized, then becomes forward-biased for a short time after switch-off. That simple detail protects the switch from an inductive voltage spike, but it also changes how quickly the relay, solenoid, or motor current decays.

Why Flyback Diodes Matter in Schematic Review

An inductor resists a sudden change in current. The magnetic energy stored immediately before turn-off is approximately E = ½LI². If the schematic opens the current path without providing a controlled alternative, the inductor raises the voltage until current finds a path through parasitic capacitance, MOSFET avalanche, insulation, an unintended IC protection structure, or an arc.

The visible symptom may be a failed transistor, MCU resets, corrupted sensor readings, EMI, contact wear, or a design that works on the bench but fails when the cable or load changes. A clean ERC result does not prove the clamp is present, correctly polarized, or fast enough for the mechanism. That is why inductive-load protection belongs in a complete schematic review checklist before PCB layout.

Nexperia’s power-switch guidance describes relays, solenoids, motors, and even long cables as inductive loads whose stored energy can damage a system when the load is disconnected. Its recommended options include a freewheeling diode across the load, a higher-voltage clamp, or a deliberately verified avalanche strategy—not simply leaving the switching device to absorb an unknown event.

Flyback Diode Schematic Checklist

Review area	What to verify	Common failure
Load and topology	DC relay, solenoid, one-direction motor, H-bridge, BLDC inverter, AC coil, or remote cable	Using the simple diode topology where current must reverse
Polarity	Cathode to positive supply; anode to the switched side for a low-side DC driver	Forward-biasing the diode whenever the load turns on
Current rating	Initial flyback current, pulse duration, repetition rate, duty cycle, and temperature	Choosing from steady-state diode current alone
Reverse voltage	Supply tolerance, transients, diode VRRM, and the switch absolute maximum	Matching the rating to nominal supply voltage with no margin
Release behavior	Allowed relay release, solenoid drop-out, or motor coast time	Adding a low-voltage diode clamp and overlooking slow release
Placement	Short loop at the load or load connector; connector polarity and remote harness behavior	Putting the clamp far from the coil so cable inductance remains outside the loop
Built-in protection	Relay, driver IC, or smart switch datasheet and polarity requirements	Duplicating or fighting an internal clamp without understanding it

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Flyback Diode Schematic: Correct Polarity

SpeedUp-generated engineering evidence: Correct flyback diode polarity for a low-side MOSFET driving a DC inductive load, with the cathode connected to positive supply. — SpeedUp-generated project evidence: This flyback diode schematic shows the diode reverse-biased during normal energization and conducting the stored coil current after the MOSFET turns off.

For the common low-side N-channel MOSFET circuit, the positive supply feeds one side of the coil and the MOSFET pulls the other side toward ground. The flyback diode goes across the coil. Its cathode connects to the supply side and its anode connects to the switched side.

While the MOSFET is on, the diode sees reverse voltage and should not conduct. At turn-off, coil current tries to keep flowing in the same direction. The switched node rises until the diode conducts, closing a local loop through the coil and diode. If the diode is reversed, it creates a near-short when the MOSFET turns on. If the diode is placed in series with the load, it does not provide the intended recirculation path.

Relays with a built-in suppression diode are polarity-sensitive even if the bare coil would not otherwise care about polarity. Check the exact orderable relay suffix and pinout before adding a second external diode or reversing the connector.

Where to Place the Diode

Place the clamp physically close to the inductive load, not merely close to the MOSFET. The goal is to make the turn-off current loop—load, diode, and short interconnect—as small as practical. Panasonic’s relay guidance recommends mounting the protective device in the immediate vicinity of the load and warns that excessive distance reduces effectiveness.

If a relay or solenoid sits off-board, put the diode at the coil or at the load-side connector when the wiring and service model allow it. A board-side clamp may still protect the switch, but the long harness remains part of the transient loop. Document connector polarity because reversing a load assembly that contains a diode can short the supply.

Placement also matters for PCB review. Keep the high-current recirculation loop out of sensitive analog ground, RF, reset, and sensor paths. Confirm copper width, diode thermal path, connector current, and return-path geometry in the KiCad schematic-to-layout checklist before routing begins.

How to Size a Flyback Diode

There is no universal “use a 1N4007” rule. A slow relay that switches a few times per minute, a PWM solenoid, and a brushed motor can place very different electrical and thermal stress on the diode.

1. Start with current at turn-off

The diode current immediately after switch-off is approximately the load current just before switch-off. Use the coil or motor operating current under worst-case supply, temperature, and load conditions—not the MCU pin current or an optimistic nominal value. Check the diode forward-current, surge-current, pulse-duration, and repetitive thermal limits.

2. Estimate stored energy and repetition

Stored inductive energy increases with the square of current: E = ½LI². A 100 mH coil carrying 200 mA stores about 2 mJ. That may be small for one event, but repetitive PWM or rapid cycling can turn pulse energy into a temperature problem. Use measured waveforms and component thermal data when switching is frequent.

3. Choose reverse-voltage margin from the real environment

While the load is on, the diode is reverse-biased by roughly the supply voltage. Supply tolerance, automotive or industrial transients, cable events, and wiring mistakes can raise the requirement. OMRON gives a simple relay-selection reference of reverse withstand voltage at least twice the supply voltage and forward current at least the load current for one of its surge-absorption examples; Panasonic publishes different guidance for some relay classes. Treat these as supplier-specific starting points and verify the diode, relay, switch, and system transient requirements together.

4. Check speed and recovery

A general-purpose rectifier can be adequate for a slowly operated DC relay, but high-frequency PWM and bridge commutation need diode recovery and switching-loss analysis. A Schottky diode has low forward voltage and little reverse-recovery charge, but its lower clamp voltage usually lets current decay more slowly, and its reverse-voltage and leakage characteristics may be limiting. “Faster diode” does not automatically mean “faster relay release.”

5. Verify the switch as part of the clamp

Check MOSFET or transistor voltage, current, safe operating area, avalanche rating, gate behavior, and driver-IC clamp structure. A MOSFET body diode is not automatically a substitute for a diode across a coil in a single low-side switch: the body diode is connected across the MOSFET, while the coil needs a complete current loop after the switch opens.

Diode, Zener, TVS, or Snubber?

SpeedUp-generated engineering evidence: Comparison of a flyback diode, diode plus Zener or TVS clamp, and bridge or inverter recirculation paths. — From the same SpeedUp project: Clamp voltage affects current-decay speed, release behavior, and switch stress; bridge-driven loads require topology-specific recirculation.

A plain diode clamps at a low voltage, so it is gentle on the switch and efficient at suppressing the spike. The tradeoff is slow current decay. Both OMRON and Panasonic warn that coil-surge suppression can lengthen relay or solenoid release time. That matters when contact timing, mechanical drop-out, valve closing, safety interlocks, or high cycling speed are important.

A diode plus Zener, TVS clamp, or another higher-voltage suppression network allows a larger voltage across the coil after turn-off. The larger voltage drives current toward zero faster, but it increases voltage stress and pulse energy in the clamp. Nexperia’s power-switch application guidance compares freewheeling, TVS-clamp, active-clamp, and MOSFET-avalanche approaches. Use the load, driver, and switch datasheets to set the allowed clamp voltage rather than choosing a Zener value from supply voltage alone.

For AC coils, a single rectifier diode across the coil would conduct on one half-cycle. OMRON recommends diode suppression as a common DC-coil approach, while varistors or CR networks are typical for AC coils. RC snubbers and MOVs may also be used for contacts or AC loads, but their values, leakage, heating, safety ratings, and failure modes need application-specific design.

Application Boundaries: Relay, Solenoid, Brushed Motor, H-Bridge, and BLDC

Application	Typical protection direction	Key review question
DC relay coil	Diode across coil; higher-voltage clamp if faster release is required	Does suppression change contact release timing or relay polarity?
DC solenoid or valve	Freewheel diode, diode-Zener, TVS, active clamp, or rated avalanche	How quickly must the actuator release, and how often does it switch?
One-direction brushed motor	Diode or clamp compatible with startup, stall, PWM, and coast behavior	Can the diode handle motor current, repetition, and required stopping time?
Bidirectional H-bridge	Bridge body diodes, external diodes, synchronous paths, TVS, and driver strategy	Where does current circulate in every switching state and direction?
Three-phase BLDC inverter	Per-switch recirculation, bus clamp, gate-drive timing, current sensing, and control	Have commutation, dead time, regeneration, and bus overvoltage been analyzed?
AC relay coil	Varistor or properly designed CR network, not one rectifier diode	Are component ratings and mains safety requirements satisfied?

Example From a Real SpeedUp Project: When One Diode Is Not Enough

SpeedUp-generated three-phase motor inverter schematic for a high-speed hair dryer. — This real SpeedUp-generated project uses a three-phase motor-inverter architecture, where current recirculation and protection must be reviewed per switching state rather than with one diode across the motor.

The three-phase motor inverter example exposes U, V, and W phase outputs, gate-control paths, current sensing, bus sensing, and fault feedback. A single flyback diode directly across this motor would conflict with bidirectional phase voltages and is not a substitute for the inverter’s MOSFET body-diode paths, external clamp choices, bus-energy handling, gate timing, and firmware.

The opposite case is also useful. SpeedUp’s desktop robot controller project explicitly notes that its current package does not contain motor drivers or actuator electronics. If a later revision adds a relay, solenoid, or brushed motor, the flyback path becomes a new schematic requirement; it should not be assumed to exist because the controller, regulator, and connectors already pass ERC.

Common Flyback Diode Mistakes

Reversing the diode: it conducts during normal operation and can short the supply through the switch.
Placing the diode in series: the inductive current still has no local loop when the switch opens.
Assuming the MOSFET body diode is enough: its orientation may not provide the required path in a single low-side driver.
Ignoring release time: a low-voltage clamp may keep a relay, contactor, valve, or solenoid energized longer than expected.
Using nominal current only: motor stall, supply tolerance, temperature, PWM, and repetitive pulses can dominate stress.
Putting the clamp far from the load: cable inductance and the enlarged loop can still generate noise and overshoot.
Using one diode on an AC or bidirectional load: the normal operating voltage reverses, so the simple topology no longer applies.
Copying a diode part number without checking its datasheet: package, leakage, VRRM, pulse current, temperature, and availability all matter.

What ERC and AI Schematic Review Can—and Cannot—Catch

ERC may flag an unconnected pin, conflicting pin types, or a missing power driver, but it normally does not know the relay’s stored energy, acceptable release time, motor stall current, harness inductance, or the MOSFET’s repetitive avalanche margin. It may also accept a diode that is electrically connected but reversed for the intended operating state.

An AI-generated schematic should therefore be treated as a first engineering draft. Ask the generator or reviewer to identify every inductive load, state the current path for switch-on and switch-off, name the suppression topology, expose component ratings, and flag unresolved release-time or safety requirements. Engineers still need to validate the schematic, layout, thermal behavior, firmware timing, sourcing, EMC, and compliance before production.

How SpeedUp Fits

SpeedUp can turn a product-level prompt into a structured schematic draft with named power, control, interface, and protection blocks. For a relay or solenoid controller, that draft should make the switch, load connector, supply, clamp, and review assumptions visible. The useful output is not an automatic promise that the diode is correct; it is an editable starting point where an engineer can verify polarity, ratings, release behavior, and PCB constraints before layout.

FAQ

What does a flyback diode do?

It provides a controlled path for inductive current after a switch turns off. This limits the voltage spike that would otherwise stress the transistor, MOSFET, driver IC, insulation, and nearby electronics.

Does every MOSFET driving a motor need a flyback diode?

Every inductive switching topology needs a valid current-recirculation and energy-management path, but that path is not always one diode across the motor. A one-direction low-side brushed-motor stage may use a diode across the motor. H-bridges and BLDC inverters use multiple switching and recirculation paths that must be analyzed for every state.

Can a Schottky diode be used as a flyback diode?

Yes, if its reverse-voltage, current, leakage, temperature, pulse-energy, and package ratings fit the circuit. Its low forward voltage reduces the clamp voltage and can slow current decay, so it is not automatically the best choice when fast relay or solenoid release matters.

Should the flyback diode be placed near the MOSFET or the coil?

Usually place it as close to the inductive load as practical so the recirculation loop is short. For a remote load, account for connector polarity and cable inductance; a board-side clamp may not eliminate the transient generated by the harness outside the local loop.

Why can a flyback diode make a relay release more slowly?

The diode clamps the coil to a low voltage after turn-off, so the current and magnetic field decay gradually. A higher-voltage diode-Zener or TVS solution can shorten release time, but the switch and clamp must be rated for the higher voltage and pulse energy.

A flyback diode is not the same as an RC network. When the problem is switch-node ringing or an underdamped parasitic resonance, use the snubber circuit design guide to estimate R and C from measurements and verify the result on hardware.

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July 23, 2026

CAN Bus Termination Resistor: 120Ω Placement and Testing

Quick Answer

SpeedUp turns a product brief for a CAN bus node into an electronics architecture for transceiver connections, bus topology, and 120-ohm termination, structured schematic sheets, and an editable KiCad project for engineering review. Review the SN65HVD230 CAN bus schematic checklist to see how termination, protection, control pins, and transceiver connections fit into a complete interface review.

A high-speed CAN bus normally uses one 120 Ω termination resistor across CANH and CANL at each physical end of the cable trunk. Intermediate nodes are normally left unterminated and connected with short stubs. The two endpoint resistors appear in parallel to the transceivers, producing a nominal 60 Ω differential load across the complete bus.

Place termination according to the physical network, not according to which controller is logically first or last. If a board may be installed at either an endpoint or a middle position, use a documented DNP, jumper-selectable, or properly designed electronic termination option. With the network de-energized and active interfaces isolated, a resistance measurement between CANH and CANL should be about 60 Ω when both 120 Ω endpoint terminations are present. That static test can find missing or extra terminators, but it cannot prove that stub length, cable impedance, bit rate, protection parts, or PCB layout are correct.

Scope: this guide addresses high-speed CAN and CAN FD physical networks based on the ISO 11898-2 style of differential twisted-pair wiring. Do not apply the same termination rules blindly to every low-speed, fault-tolerant, single-wire, or application-specific CAN physical layer.

Why CAN Bus Termination Matters

A CAN cable behaves as a transmission line when signal-edge travel time is significant relative to the bit timing. An impedance discontinuity at an unterminated cable end reflects part of the signal back toward the transmitter. The result can be ringing, delayed threshold crossings, extra edges, intermittent errors, or a network that works on a short bench harness but fails after the cable, node count, temperature, or data rate changes.

The termination resistance is chosen to match the cable’s characteristic impedance. For conventional high-speed CAN, the common target is 120 Ω. The CAN in Automation high-speed transmission guidance recommends a line topology terminated at both ends with 120 Ω resistors matching the cable. Texas Instruments shows the same standard and split termination arrangements in its CAN physical-layer application report.

Termination is also a load. Two 120 Ω resistors in parallel produce 60 Ω across CANH and CANL. Adding a third 120 Ω termination lowers the equivalent resistance to 40 Ω, while four lower it to 30 Ω. That extra load can reduce the dominant differential voltage and push the transceiver outside the conditions under which its output performance is specified. More termination is not safer.

CAN Bus Termination Checklist

Review area	What to check	Why it matters
Physical layer	Confirm that the network is high-speed CAN or CAN FD and identify the governing system profile.	Other CAN physical layers can use different wiring and termination.
Cable impedance	Verify the cable or harness characteristic impedance and connector assumptions.	Termination should match the transmission line; 120 Ω is common, not a magic value detached from the cable.
Topology	Identify the two physical ends of the trunk and every stub.	Passive star branches and long stubs introduce additional reflection points.
Endpoint resistors	Fit one 120 Ω differential termination at each physical end.	The complete bus then presents a nominal 60 Ω differential load.
Intermediate nodes	Normally leave them unterminated and keep their stubs short.	Termination at every node overloads the bus and does not remove stub reflections.
Removable nodes	Ensure removing an endpoint device does not accidentally remove required cable termination.	A network may become unterminated during service or reconfiguration.
Termination type	Choose standard, split, jumper-selectable, or electronic termination deliberately.	Each option has BOM, EMC, reliability, and configuration consequences.
Power rating	Check resistor voltage, pulse, temperature, and fault dissipation against the transceiver and system.	Cable shorts to higher-voltage rails can exceed normal communication dissipation.
Test access	Provide safe access to CANH, CANL, and ground at representative network points.	Resistance and oscilloscope checks should not require improvised probing.
Documentation	Record which installation positions require termination and the default assembly state.	A correct schematic can still be assembled or configured incorrectly.

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CAN Termination Resistor Schematic Patterns

A CAN termination resistor schematic should make the board’s physical role obvious before layout or assembly. Show the terminator between the named CAN_H and CAN_L nets, then document whether it is fitted, not fitted, or selectable by default. The correct choice follows the two physical ends of the cable, not the number of nodes on the network.

Board role	Schematic implementation	Default assembly state	Evidence a reviewer should see
Dedicated endpoint	One 120 Ω resistor, usually named RTERM, directly between CAN_H and CAN_L	Fitted	Named bus nets, resistor value, and an endpoint note
Endpoint or intermediate node	120 Ω resistor controlled by a solder jumper, removable shunt, or explicit DNP option	Documented as fitted or open for the intended product configuration	Jumper state, BOM/DNP state, and an assembly note that agrees with the schematic
Split-termination endpoint	Two approximately 60 Ω resistors in series across CAN_H and CAN_L, with the midpoint capacitor chosen from transceiver guidance	Fitted only when split termination is part of the EMC strategy	Matched resistor values, midpoint capacitor value, return path, and supporting transceiver guidance
Software-selectable endpoint	A reviewed switch topology that inserts or removes the termination network	Safe and defined during reset and while the board is unpowered	Switch ratings, control default, leakage path, and failure-state behavior

For a reusable node, a selectable 120 Ω footprint is usually easier to review than an unexplained fixed resistor. The schematic, BOM, assembly drawing, and setup instructions should all state the same default so a middle node is not accidentally shipped with termination enabled.

Where to Place the Two 120 Ω Resistors

Place the resistors at the two farthest physical ends of the main CAN trunk. They can be inside the endpoint nodes or in dedicated cable terminators. What matters is that the transmission line actually ends at each resistor and that both terminations remain present in every supported configuration.

SpeedUp-generated engineering evidence: Correct linear CAN bus with 120 ohm termination at each physical end compared with an incorrectly terminated star network. — SpeedUp-generated project evidence: Termination follows the ends of the physical cable trunk. Intermediate nodes normally use short, unterminated stubs; putting 120 Ω at every branch adds load without converting a passive star into a clean line.

The logical order of CAN identifiers, arbitration priority, or software roles does not determine termination. A gateway, motor controller, sensor, or diagnostic tool needs termination only when its connector is at a physical end of the active network. A node located in the middle of the harness normally does not need 120 Ω even if it is the application master.

Stub length deserves its own timing review. There is no single safe stub length for every CAN or CAN FD design because the limit depends on edge rate, arbitration and data bit rates, cable delay, transceiver timing, node loading, connectors, and topology. Keep stubs as short as practicable and validate the actual network rather than copying a universal number from a forum.

Standard vs Split CAN Termination

Standard termination is one resistor, typically 120 Ω, directly between CANH and CANL at an endpoint. Split termination replaces it with two matched resistors, typically 60 Ω each, connected in series between CANH and CANL. Their midpoint connects to ground through a capacitor. The differential DC resistance remains about 120 Ω at that endpoint.

SpeedUp-generated engineering evidence: Standard 120 ohm CAN termination compared with split termination using two 60 ohm resistors and a midpoint capacitor. — From the same SpeedUp project: Standard and split endpoint networks both present approximately 120 Ω differentially. Split termination adds a common-mode path through the midpoint capacitor.

Split termination can stabilize and filter common-mode voltage and improve emissions behavior. It does not compensate for an incorrect topology or missing endpoint. The TI TCAN1043-Q1 datasheet shows two 60 Ω resistors and notes a typical 4.7 nF split capacitor, with values up to 100 nF in that device’s guidance. Treat those figures as vendor guidance for a particular implementation, not as universal values for every transceiver, cable, ground strategy, or EMC target.

Match the two split resistors closely, place the network as the transceiver or system reference recommends, and evaluate the capacitor return path. The midpoint is a common-mode filter node, not permission to connect noisy chassis, digital, or isolated grounds together without reviewing the isolation and EMC architecture.

Fixed, Jumper-Selectable, and Electronic Termination

Fixed termination is the most predictable choice when a product is always installed at one end of the bus. If the same PCB can appear at an endpoint or in the middle, adding a DNP resistor footprint or jumper-selectable termination can reduce assembly variants. The configuration must be visible in the schematic, assembly documentation, enclosure labeling, and test plan.

A solder jumper is appropriate only when infrequent configuration is acceptable. Review the SpeedUp guide to solder jumpers in KiCad schematics for labeling, default state, assembly access, and documentation considerations. A removable shunt or switch is easier to service but introduces its own connector, contact, and user-error risks.

Software-controlled termination is possible when identical nodes must be dynamically assigned as endpoints. It is not simply a GPIO placed in series with a random analog switch. Switch on-resistance, parasitic capacitance, fault voltage, unpowered behavior, isolation, default state, and failure mode all matter. Texas Instruments’ TIDA-01238 selectable CAN termination reference design and isolated CAN design guidance show reviewed approaches and explain why only the two farthest nodes should enable their 120 Ω networks.

How to Test CAN Bus Termination Resistance

Never use an ohmmeter on an energized or actively switching bus. Follow the equipment’s safe shutdown procedure, remove power from the network, discharge stored energy where applicable, and isolate or disconnect active CAN interfaces as the system documentation requires. Then measure resistance directly between CANH and CANL from an accessible connector. The TI CAN EVM user’s guide uses two 120 Ω resistors in parallel to represent the standard 60 Ω bus load for electrical measurements.

SpeedUp-generated engineering evidence: Ohmmeter measuring approximately 60 ohms between CANH and CANL on a de-energized network with two 120 ohm terminators. — SpeedUp engineering output: A de-energized network with two healthy 120 Ω endpoint terminations should measure close to 60 Ω between CANH and CANL. Real readings include resistor tolerance and other connected components.

Approximate reading	Likely interpretation	Next check
About 60 Ω	Two 120 Ω endpoint networks are probably present.	Confirm their physical locations and then test the active waveform.
About 120 Ω	Only one endpoint termination may be enabled or connected.	Inspect the opposite endpoint, cable, connector, jumper, and assembly state.
About 40 Ω	Three 120 Ω terminations may be present in parallel.	Find the unintended termination; do not assume the lower resistance is beneficial.
Very high or open	No complete differential termination path is visible from the measurement point.	Check both endpoints, cable continuity, connectors, and measurement isolation.
Unexpected or unstable	The network may still be powered, connected electronics may influence the reading, or protection/switching circuits may be involved.	Stop and verify the safe test state and schematic before drawing a conclusion.

A correct 60 Ω reading does not prove the network is healthy. It cannot reveal an endpoint resistor located at the end of a long branch instead of the trunk, excessive stub length, a poor cable, connector discontinuity, marginal transceiver timing, asymmetric protection capacitance, or ringing at the selected bit rate. Use an oscilloscope or appropriate CAN analysis equipment to inspect CANH, CANL, and differential behavior at representative near and far nodes while the final harness and node population are operating.

Example From a SpeedUp CAN Schematic Review

The existing SN65HVD230 CAN bus schematic checklist treats termination as a system decision rather than a resistor copied from a breakout board. A reviewer first asks whether the board is always an endpoint, sometimes a middle node, or a diagnostic adapter. That answer determines whether the schematic should show a fixed 120 Ω resistor, a split network, a selectable option, or no fitted termination.

For an SN65HVD230 or another CAN transceiver, the review must continue beyond termination. Check the transceiver supply and decoupling, MCU TXD/RXD connections, standby or slope-control behavior, CANH/CANL connector mapping, protection, common-mode and fault limits, test points, and whether the selected device supports the required CAN or CAN FD application. The termination guide and the transceiver checklist have different primary search intents, but together they describe a more complete interface review.

CAN Node Schematic Decision Table

Decision	Endpoint implementation	Intermediate-node implementation
Termination state	120 Ω fitted, or the termination option enabled	Termination omitted, DNP, or the option left open
Connection to the trunk	Placed at the physical cable end	Connected with the shortest practical stub for the data rate and network timing
Protection and transceiver	Selected for the bus voltage, fault, ESD, and common-mode requirements	The same electrical checks still apply; removing termination does not remove the need for protection
Documentation	Assembly notes identify the board as an endpoint and state the enabled default	Assembly notes state that termination is disabled unless the board becomes a cable endpoint
Bench resistance check	A fully assembled, unpowered network with both endpoints connected should measure about 60 Ω between CAN_H and CAN_L	The node alone should not add another 120 Ω path across the bus

This decision is a system-level property. Two identical boards may need different termination states when one is installed at a cable end and the other is installed in the middle of the same network.

Common CAN Termination Mistakes

Placing 120 Ω on every CAN transceiver because every reference schematic contains an optional footprint.
Choosing termination from the logical controller hierarchy instead of the physical cable ends.
Removing an endpoint device and unintentionally removing one of the two required terminators.
Using a passive star and assuming extra termination resistors will eliminate every branch reflection.
Copying a split capacitor value without checking the transceiver data sheet, EMC target, grounding, and isolation architecture.
Ignoring resistor voltage and power behavior during cable-to-supply or cable-to-ground faults.
Measuring resistance while the network is energized or data is active.
Treating a 60 Ω multimeter reading as proof that the active CAN waveform and CAN FD timing are valid.
Moving to layout without documenting default jumper state, DNP parts, connector role, and endpoint assumptions.

How SpeedUp Fits

SpeedUp can turn a product requirement into a structured KiCad schematic draft that shows the MCU or CAN controller, transceiver, CANH/CANL connector, candidate protection, termination option, control pins, test points, and design notes in one reviewable interface block. A useful prompt should state the expected network position, cable or connector, CAN or CAN FD rate, supply domains, isolation needs, protection environment, and whether termination must be fixed or configurable.

The generated result is a first engineering draft, not a production-ready reference design. Engineers still verify the physical-layer standard, transceiver data sheet, topology, cable, bit timing, termination and protection networks, resistor ratings, isolation, PCB layout, firmware configuration, sourcing, safety, compliance, manufacturing, and hardware test results. Use the broader schematic review checklist before PCB layout to document those decisions.

Related SpeedUp Guides

What to check before using an AI-generated KiCad schematic for PCB layout — downstream review for footprints, layout constraints, validation gaps, and release readiness.

FAQ

Does a CAN bus need a termination resistor?

A conventional high-speed CAN or CAN FD line normally needs termination at both physical ends. Confirm the actual physical-layer standard and system profile because not every CAN implementation uses the same network.

Why does CAN bus use 120 Ω resistors?

The resistance is selected to match the characteristic impedance of the commonly specified high-speed CAN twisted-pair cable. Matching the cable ends reduces reflections. The value is about the transmission line, not a pull-up or pull-down requirement of the logic pins.

What Are CAN_H and CAN_L?

CAN_H and CAN_L are the two conductors of the differential high-speed CAN physical layer. During a dominant bit, CAN_H rises and CAN_L falls relative to their recessive common-mode level, and the receiver responds to the voltage difference between them. Termination connects between CAN_H and CAN_L at the two physical ends of the bus—not from either signal to ground. Exact voltage, common-mode, and fault limits depend on the selected transceiver and CAN physical-layer standard.

How many 120 Ω termination resistors should a CAN bus have?

A standard linear high-speed CAN bus normally has two: one at each physical end of the trunk. Intermediate nodes normally do not fit 120 Ω termination.

What resistance should I measure between CANH and CANL?

With the network safely de-energized and active interfaces isolated, two 120 Ω endpoint resistors in parallel should measure approximately 60 Ω, allowing for tolerance and other connected circuitry. About 120 Ω often suggests one missing endpoint, while about 40 Ω can suggest three parallel 120 Ω terminations.

Can the termination resistor be placed on the PCB?

Yes, if that PCB is genuinely at the physical end of the active cable. If the board can be removed or used in the middle of the network, make termination selectable or place it in the cable so that the required endpoint terminations remain present.

Is split termination always better than one 120 Ω resistor?

Not automatically. Split termination can improve common-mode stabilization and emissions, but it adds components and a grounding-dependent capacitor path. Use the transceiver vendor’s guidance and validate the final network and EMC behavior.

Can a 60 Ω resistance test confirm CAN FD signal integrity?

No. It confirms only the approximate static differential resistance seen from the measurement point. CAN FD performance still depends on data-phase timing, cable and connector impedance, stub length, transceivers, protection components, layout, node count, and active waveform quality.

Termination is only one physical-layer decision. For controller-side SPI, oscillator, interrupt, and transceiver integration, continue with the MCP2515 CAN controller schematic checklist.

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July 22, 2026

I2C Pull-Up Resistor Values: Calculation and PCB Design Checklist

Quick Answer

SpeedUp converts product requirements for an I2C bus into an electronics architecture covering logic voltage, bus capacitance, speed, pull-up values, and device connections, structured schematic sheets, and an editable KiCad project for engineering review. Explore the SpeedUp Demo: Temperature and Humidity Sensor to see this handoff in a real project.

An I2C pull-up resistor cannot be chosen from bus speed alone. Start by calculating a minimum resistance from the supply voltage, the maximum valid LOW voltage, and the weakest device’s sink-current capability. Then calculate a maximum resistance from the allowed rise time and the total bus capacitance. Choose a standard value between those limits and verify the real SDA and SCL rise times on the assembled board.

A 4.7 kΩ resistor is a common starting point for a short 3.3 V, 100 kHz bus, but it is not a universal answer. A 400 kHz bus with 200 pF of capacitance may need a value around 1 kΩ to 1.8 kΩ, while a short low-capacitance bus may work with a larger value. Also count every pull-up already fitted on sensor modules, displays, level shifters, and development boards because parallel resistors reduce the effective resistance.

Why I2C Needs Pull-Up Resistors

I2C devices normally use open-drain or open-collector outputs on SDA and SCL. A device can pull a line LOW, but it does not actively drive the line HIGH. A pull-up resistor returns the line to the bus supply when every connected device releases it. This wired-AND behavior lets multiple devices share the same two signals and supports arbitration and clock stretching.

The resistor creates an engineering trade-off. A smaller resistance charges the bus capacitance faster and produces a sharper rising edge, but it also requires more sink current whenever the line is LOW. A larger resistance reduces LOW-state current but produces a slower edge. If the edge does not reach a valid HIGH before the next transition, the bus can produce intermittent acknowledgments, corrupted transfers, or failures that appear only with certain cables, temperatures, probes, or device combinations.

I2C Pull-Up Resistor Calculator Formulas

The official NXP I2C-bus specification and TI pull-up resistor calculation note define the same two boundaries.

Maximum resistance from rise time

R_p(max) = t_r(max) / (0.8473 × C_b)

t_r(max) is the maximum permitted rise time for the selected I2C mode.
C_b is the total capacitance on one bus line, including device pins, PCB traces, connectors, cables, level shifters, and measurement probes.
The factor 0.8473 comes from the time required for an RC waveform to rise from 30% to 70% of the bus voltage.

Minimum resistance from sink current

R_p(min) = (V_DD - V_OL(max)) / I_OL

V_OL(max) and I_OL must come from the bus specification and the data sheets for the actual controller, targets, level shifters, and buffers. The weakest device on the bus sets the practical limit. Do not assume every device can sink the Fast-mode Plus current simply because the controller supports a 1 MHz clock.

Rise-Time Limits and Calculated Maximum Values

NXP specifies different maximum rise times for the common I2C modes. The table below also shows the maximum pull-up resistance calculated for several estimated bus capacitances. These are mathematical upper limits, not automatic production choices.

Mode	Nominal maximum rate	Maximum rise time	R_p(max) at 50 pF	R_p(max) at 100 pF	R_p(max) at 200 pF
Standard-mode	100 kbit/s	1000 ns	23.6 kΩ	11.8 kΩ	5.90 kΩ
Fast-mode	400 kbit/s	300 ns	7.08 kΩ	3.54 kΩ	1.77 kΩ
Fast-mode Plus	1 Mbit/s	120 ns	2.83 kΩ	1.42 kΩ	0.71 kΩ

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At 400 pF, the calculated Fast-mode maximum is about 0.89 kΩ. A 3.3 V device limited to a 3 mA LOW-state sink current may require roughly 0.97 kΩ or more. That leaves no valid worst-case resistor range. The fix is not to pick an impossible value between the limits; reduce capacitance, lower the bus speed, use devices with appropriate drive capability, divide the bus with a buffer, or redesign the interconnect.

Worked Example: 3.3 V, 400 kHz, 200 pF

This example follows the values used in the TI application note:

V_DD = 3.3 V
V_OL(max) = 0.4 V
I_OL = 3 mA
C_b = 200 pF
t_r(max) = 300 ns for Fast-mode

The minimum resistance is (3.3 - 0.4) / 0.003 = 967 Ω. The maximum resistance is 300 ns / (0.8473 × 200 pF) = 1.77 kΩ. A standard value such as 1.2 kΩ or 1.5 kΩ may fit the calculated window, subject to every device’s actual data sheet and the measured bus waveform. A 4.7 kΩ resistor is outside this Fast-mode example’s calculated upper limit.

Worked Example: 3.3 V, 400 kHz, 100 pF

With the same voltage and sink-current assumptions but half the capacitance, the minimum remains approximately 967 Ω and the maximum becomes 3.54 kΩ. Values such as 1.5 kΩ, 2.2 kΩ, or 3.3 kΩ may fit the calculation. The final choice depends on power, noise margin, device limits, and measured rise time.

This example explains why 2.2 kΩ is common on compact 400 kHz sensor buses while 4.7 kΩ may still be suitable for a shorter 100 kHz bus. The clock label alone is insufficient; capacitance changes the answer.

Parallel Pull-Ups on Modules and Development Boards

A bus has one effective pull-up resistance per line, even if the schematic contains several physical resistors. Parallel resistors combine as:

1 / R_effective = 1 / R₁ + 1 / R₂ + ... + 1 / R_n

Two 4.7 kΩ pull-ups in parallel become 2.35 kΩ. Four modules with 10 kΩ pull-ups become 2.5 kΩ. That lower effective resistance may improve rise time, but it also increases sink current. Audit breakout boards, displays, sensor modules, debug adapters, and level-shifter boards instead of assuming the two resistors visible on the main schematic are the whole bus.

Power Consumption and Battery Designs

The approximate current through one pull-up while its line is LOW is (V_DD - V_OL) / R_p. Ignoring the small LOW voltage for a quick estimate, a 4.7 kΩ resistor at 3.3 V draws about 0.70 mA while the line is LOW; a 2.2 kΩ resistor draws about 1.5 mA. Average current depends on bus activity and the fraction of time SDA and SCL remain LOW.

For a battery-powered sensor, the answer is not automatically to use a very large resistor. Slow edges can cause retries, keep devices active longer, or fail at the target speed. Use the highest resistance that still meets worst-case timing and noise requirements, then confirm sleep behavior, bus-idle states, pull-ups on powered-down modules, and possible back-power paths. The broader battery-powered sensor circuit checklist covers the surrounding power-budget review.

Example From Real SpeedUp-Generated Schematics

The SpeedUp smart-ring circuit example places an nRF52832, MAX30102 optical sensor, and BMI270 IMU on a shared I2C architecture. It is a useful pull-up review case because a compact battery product combines several bus devices, strict power targets, and a small PCB where the schematic can look simple even though the electrical constraints interact.

SpeedUp-generated nRF52832 smart-ring schematic with I2C signals and pull-up resistors. — SpeedUp-generated project evidence: The nRF52832 MCU sheet exposes the shared I2C nets and pull-ups that connect the smart ring’s optical and motion sensors. The resistor values still need review against bus capacitance, speed, device limits, and power budget.

A second example comes from the temperature and humidity sensor KiCad project. Its CHT20MEMS sensor connects to a 3.3 V I2C bus shared with the controller/display subsystem. The generated sheet makes the rail and bus names visible, but the engineer still has to confirm where the effective pull-ups live, whether the display module adds another pair, and whether the chosen values work at the intended clock rate.

SpeedUp-generated CHT20 temperature and humidity sensor schematic on a 3.3 V I2C bus. — From the same SpeedUp project: This real sensor sheet shows the CHT20MEMS rail and I2C connections. Pull-up calculation must include the controller, display, sensor, PCB, connectors, and any module resistors on the complete bus.

KiCad I2C Pull-Up Review Checklist

Review area	What to check	Why it matters
Bus voltage	Pull SDA and SCL to a voltage compatible with every connected pin.	A pull-up to the wrong rail can violate input limits or back-power an unpowered domain.
Clock mode	Document 100 kHz, 400 kHz, 1 MHz, or the actual operating range.	The allowed rise time changes with the selected mode.
Bus capacitance	Estimate IC pins, traces, branches, connectors, cables, shifters, and probes.	Capacitance sets the maximum usable pull-up resistance.
Sink capability	Check `V_OL` and `I_OL` for every bus device.	The weakest output determines the minimum safe resistance.
Parallel resistors	Audit pull-ups on modules and calculate their effective parallel value.	Several harmless-looking module pull-ups can create excessive sink current.
Power states	Review reset, sleep, switched rails, and partially powered devices.	The bus can leak current or back-power devices when rails turn off in different states.
Configuration options	Consider DNP options or alternate footprints when bus loading is uncertain.	Bring-up can tune the value without cutting traces.
Measurement access	Add accessible SDA, SCL, ground, and bus-voltage test points.	The final value should be validated on the real board with the intended devices connected.
Review record	Write the selected speed, estimated capacitance, calculation, and assumptions in design notes.	A documented choice is easier to revisit when the bus or enclosure changes.

How to Validate the Value on Hardware

Populate the intended production device set, including displays, sensor modules, cables, and level shifters.
Measure both SDA and SCL at the worst expected bus speed and supply voltage.
Measure rise time between 30% and 70% of the bus voltage. Account for oscilloscope-probe capacitance.
Confirm the LOW voltage at the device with the weakest sink capability.
Repeat across power states, temperature range, cable options, and maximum device population.
Check for ringing, noise, slow plateaus from level shifters, clock stretching, and unexpected pull-ups.
Update the schematic and BOM with the validated value and the assumptions behind it.

The calculation narrows the design space; the assembled board confirms it. This is part of the broader AI-generated KiCad schematic review process before layout or release.

Common Mistakes

Using 4.7 kΩ automatically without calculating bus capacitance and rise time.
Using MCU internal pull-ups as the only pull-ups without checking their value, tolerance, and timing.
Forgetting that every breakout board may add another resistor pair.
Pulling the bus to 5 V when one or more pins are not 5 V tolerant.
Assuming controller support for 1 MHz means every target and level shifter supports Fast-mode Plus.
Ignoring cables, connectors, long branches, and probe capacitance.
Checking SDA but not SCL, or testing only at room temperature with one device fitted.
Treating a schematic calculation as proof that the routed, assembled bus will pass.

What SpeedUp Generates Before Engineering Review

SpeedUp can turn a product requirement into a structured KiCad schematic draft with named I2C nets, sensor and display sheets, candidate pull-ups, power domains, test points, and design notes. That makes the interface visible enough for an engineer to apply the calculation and review the whole bus instead of copying a disconnected breakout-board circuit.

The generated result is a first engineering draft, not a production-ready reference design. Engineers still verify each device data sheet, calculate and measure pull-ups, validate voltage domains and power states, review footprints and PCB layout, write firmware, test signal integrity, and complete sourcing, safety, compliance, and manufacturing work.

Product boundary: For an I2C product, SpeedUp can expose the bus devices, voltage domains, candidate pull-ups, named nets, and component context in structured schematic sheets and an editable KiCad first draft. It does not calculate away every timing and loading uncertainty or replace oscilloscope measurements, datasheet review, firmware checks, PCB layout, or production validation; engineers still close those decisions. See the SpeedUp AI schematic generator workflow for the complete product-brief-to-editable-project path.

Related SpeedUp Projects and Guides

BME280 KiCad schematic and I2C sensor checklist — interface mode, address, pull-ups, sensor placement, and footprint review.
AI-generated KiCad schematic checklist before PCB layout — downstream checks after the interface and resistor values have been reviewed.

FAQ

Do I need pull-up resistors for I2C?

Yes, a normal I2C bus needs SDA and SCL pulled HIGH because connected devices normally use open-drain or open-collector outputs. Some modules already contain pull-ups, so verify the complete bus before adding another pair.

What size pull-up resistor should I use for I2C?

Calculate the allowed range from supply voltage, LOW-level sink capability, bus capacitance, and maximum rise time. Values from about 1 kΩ to 10 kΩ are common in compact systems, but no single value is correct for every bus.

Is 4.7 kΩ always correct for I2C?

No. It is a common starting value for short, moderate-speed buses, but it can be too large for a high-capacitance 400 kHz bus or unnecessarily small for a low-power, low-speed bus. Calculate and measure instead of relying on the convention.

Can I use the microcontroller’s internal pull-ups?

Internal pull-ups are often relatively weak and have broad tolerance. They may be useful for a controlled low-speed case, but they should not be assumed to meet I2C rise-time requirements without checking the MCU data sheet and measuring the complete bus.

Where should I place I2C pull-up resistors?

A short PCB bus normally needs one effective pull-up pair, often placed near the controller or a central bus point for clarity and tuning access. Electrical performance depends on the full interconnect, branches, capacitance, and device population; placement alone does not repair an overlong or overloaded bus.

How do multiple I2C pull-ups combine?

They combine in parallel. Two 4.7 kΩ resistors produce an effective resistance of 2.35 kΩ, while four 10 kΩ resistors produce 2.5 kΩ. Include all fitted modules and development boards in the calculation.

Start Your I2C Hardware Project

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July 21, 2026

USB-C Schematic Checklist Before PCB Layout: Power, Data, and Charging

Quick Answer

SpeedUp starts with a product brief for a USB-C power or data interface, maps connector roles, CC pins, data protection, power delivery, and layout constraints into the electronics architecture, and delivers structured schematic sheets with an editable KiCad project for engineering review. The SpeedUp Demo: 100W Desktop Charging Station shows the same workflow with concrete engineering artifacts.

A USB-C schematic is ready for PCB layout only after the port role is explicit and every signal has been reviewed against that role. Start by deciding whether the receptacle is a 5 V power sink, a USB 2.0 device, a power source, a dual-role port, or a USB Power Delivery port. Then check both CC pins, VBUS protection and current assumptions, D+ and D- routing when data is present, connector shield and ESD strategy, charger and battery boundaries, symbols, footprints, connectivity, test access, and layout constraints.

Do not treat the USB-C connector as a drop-in replacement for Micro-USB. The connector shape does not tell a source what power role the product needs, and USB-C does not automatically mean USB PD or battery charging. A generated or copied circuit can look complete while missing a CC resistor, using the wrong connector pin mapping, assuming unavailable current, or connecting a charger without a defined system power path. Use this checklist together with the broader schematic review checklist before PCB layout.

First Decide What the USB-C Port Must Do

The correct USB-C circuit depends on the product role. Write the role beside the connector in the schematic instead of leaving the reviewer to infer it.

Port requirement	Schematic implication	Main review risk
5 V sink, no data	Two valid Rd terminations on CC1 and CC2, protected VBUS input, and a power path sized for the current the source actually advertises.	Assuming VBUS or high current will be available without a valid Type-C connection.
USB 2.0 device and 5 V sink	Sink detection plus the correct receptacle D+ and D- pin pairing, ESD protection, and routing to a USB PHY or bridge.	Broken cable-orientation support, long stubs, or an unprotected data pair.
5 V source	Rp presentation or a CC controller, controlled VBUS switching, current limiting, discharge behavior, and fault protection.	Driving an unsafe or uncontrolled VBUS source.
Dual-role port	A suitable CC/role controller and a power architecture that safely changes between sink and source behavior.	Conflicting power paths or the wrong role after attachment.
USB PD sink or source	A USB PD controller, negotiated power contract, protected power path, firmware or configuration, and parts rated for every supported voltage and current.	Treating a USB-C receptacle as if it automatically negotiates higher voltage or power.

Choose Your USB-C Circuit Path

Use this page as the main USB-C circuit-design guide, then open the focused resource that matches the subsystem you are building. Each child page owns a narrower component or project intent, while this hub keeps the complete connector, power, data, protection, and charging path in one place.

Design task	Use this focused resource	What it adds to the USB-C review
Protect USB 2.0 D+ and D-	USBLC6-2SC6 USB ESD protection checklist	Six-pin flow-through mapping, VBUS and ground clamp paths, connector placement, and differential routing.
Add a USB-to-UART or I2C bridge	MCP2221A bridge schematic checklist	Bridge power mode, VUSB, D+/D-, UART direction, I2C pull-ups, reset, and package decisions.
Study a USB-C debug subsystem	nRF54L15 development-board KiCad project	A real generated sheet combining the connector, CC resistors, protection, bridge, and debug header.
Connect USB-C input to charging and a battery-powered product	Temperature and humidity sensor KiCad project	A complete product example with USB-C input, battery charging, regulation, sensing, display, and BOM context.

Adding USB-C power, data, or charging?

Describe the port role, source or sink behavior, USB data speed, charging path, protection, connectors, and operating states. Create a free account to start a reviewable, editable KiCad first draft.

Start a USB-C hardware project free

USB-C names the connector and Type-C connection behavior. USB PD is a separate protocol used when the design needs negotiated power capabilities. A battery charger is another separate function: it controls the cell charge process after the input power path has been established.

USB-C Schematic Checklist

Review area	What to check in the schematic	Why it matters before layout
Port role	Label sink, source, dual-role, USB 2.0, SuperSpeed, or USB PD requirements explicitly.	The CC circuit, VBUS switch, data path, controller, and firmware all depend on the role.
Connector symbol	Verify every receptacle pin, duplicated VBUS/GND pins, CC1/CC2, D+/D- orientation pins, shield, and unused SuperSpeed pins.	Generic or simplified symbols can hide pins that matter electrically or mechanically.
CC1 and CC2	Use the correct separate termination or controller connection on both CC pins. Confirm value, tolerance, role, and controller supply state.	The port may fail in one cable orientation or never establish a valid connection.
VBUS availability	Document when VBUS may appear, the allowed input range, current advertisement handling, and what happens during disconnect or role change.	An always-on or overdrawn power path can create interoperability and safety problems.
Protection	Select ESD, overvoltage, overcurrent, reverse-current, inrush, and short-circuit protection appropriate to the role and environment.	A connector is a direct path for cable transients, user ESD, and wiring faults.
USB 2.0 data	Confirm the receptacle D+ and D- pairs are combined correctly for both orientations and routed to the intended USB PHY.	Incorrect pairing or stubs can produce orientation-dependent failures or poor signal integrity.
Data protection and series parts	Validate low-capacitance ESD parts, any series resistors, common-mode choke assumptions, and placement notes against the PHY guidance.	Protection capacitance and routing can degrade the USB data eye.
Shield and ground	Define the connector shield connection, chassis or digital ground relationship, ESD return path, and mechanical tabs.	An improvised shield path can worsen ESD and EMI behavior.
Charger boundary	Separate Type-C attachment/current handling from battery charge current, termination, thermal limits, protection, and cell requirements.	The USB input and battery charger solve different problems.
System power path	Decide whether the product runs while plugged in, how the load is isolated or shared, and how the battery and system rail interact.	System load can disturb charge termination, create reverse current, or exceed the source budget.
Capacitance and inrush	Review VBUS capacitance, hot-plug behavior, load switch or power-path needs, and discharge requirements.	Large downstream capacitance can violate attach behavior or cause unstable hot plugging.
Footprint and mechanics	Match the exact receptacle MPN, pin numbering, pad layout, shell stakes, board-edge position, mating clearance, and insertion loads.	A correct symbol with the wrong footprint still produces a failed board.
Connectivity and test access	Review power-source ownership, no-connect flags, shield pins, controller states, and add useful VBUS, CC, D+/D-, battery, and ground test points.	Explicit signal ownership and accessible measurement nodes make interface assumptions easier to verify during bring-up.

1. Check CC1 and CC2 Before Anything Else

The CC pins establish attachment, orientation, and available current information. For a simple 5 V sink-only receptacle without USB PD, Texas Instruments describes using a separate 5.1 kΩ Rd resistor from each CC pin to ground in the simplest implementation. Both pins matter because a reversible cable presents its active CC connection on one side or the other. Do not replace the two terminations with one shared resistor, and do not leave one CC pin floating.

That simple circuit is not a universal answer. The TI USB Type-C and USB Power Delivery engineering guide notes that system capacitance, data requirements, and port role can require a CC controller and controlled power path. A source presents Rp rather than Rd. A dual-role or PD port needs appropriate controller behavior. The schematic should therefore state why the chosen CC implementation is valid for this exact product.

Also separate connection detection from current budgeting. A sink must not assume that every USB-C source permits the same current. If firmware or hardware cannot interpret source current advertisement, design conservatively or add a suitable controller.

2. Review VBUS, Protection, and Hot-Plug Behavior

Trace VBUS from every receptacle pin to the first protected system node. The path may need ESD protection, overvoltage protection, current limiting, reverse-current blocking, a fuse or resettable protector, a load switch, discharge control, and input capacitance selected for the actual port role. Do not scatter those functions across sheets without showing the intended sequence.

For a minimal sink, TI’s guide calls out an additional constraint: if the capacitance presented on VBUS exceeds 10 µF, the design may need to isolate the extra capacitance behind a connection-controlled power path. Treat that as a review trigger, not as permission to copy one universal load-switch circuit. Confirm the latest requirements, the chosen controller guidance, and the behavior of the complete product.

Add notes that the PCB designer can act on: place connector protection close to the entry point, keep the surge and ESD return path short, size copper for current and temperature rise, and keep sensitive analog or RF circuits away from the cable entry and switching power path.

3. Treat USB 2.0 Data as a Reversible Interface

A USB-C receptacle exposes USB 2.0 D+ and D- pins for both plug orientations. In a USB 2.0-only implementation, the corresponding receptacle pins are normally joined near the connector so the USB PHY sees one differential pair regardless of cable orientation. Verify the exact connector symbol and follow the PHY or reference-layout guidance; do not create long branches that behave like stubs.

Review the data path from connector to device: ESD array pinout and capacitance, series components if recommended, pair continuity, length mismatch, vias, reference plane, return-path interruptions, test pads, and routing through any bridge or hub. A schematic cannot prove signal integrity, so transfer the impedance, placement, and routing constraints into the PCB layout notes.

If the product needs USB 3.x, Alternate Mode, or cable e-marker support, the design becomes more complex. SuperSpeed lanes, orientation multiplexing, VCONN, retimers or redrivers, and controller configuration should not be approximated by extending a USB 2.0 circuit.

4. Separate the USB-C Input From the Battery Charger

The Type-C port establishes an input-power relationship. The charger manages a specific battery chemistry, charge voltage, current, termination, temperature, and safety boundary. Put both functions on the same review path, but do not collapse them into one block labeled “USB charging.”

For example, the MCP73831 is a linear single-cell charger with programmable current and thermal regulation. Its datasheet specifies a programmable charge-current range from 15 mA to 500 mA, but that does not mean every USB-C source, cell, package, enclosure, or PCB can safely support 500 mA. Use the current Microchip MCP73831 family datasheet, the battery documentation, source-current handling, and thermal analysis together. The related MCP73831 charger schematic checklist covers charge current, battery connector, STAT, heat, and load-sharing questions in more detail.

Decide what happens while the product is plugged in. If the system load shares the battery node, it can affect charge termination and thermal behavior. If the product must run and charge at the same time, document the power-path or load-sharing solution rather than assuming the charger IC solves it automatically.

Example From a Real SpeedUp Project

The nRF54L15 development-board KiCad project contains a generated USB-C debug sheet with a 16-pin Type-C receptacle, separate 5.1 kΩ CC terminations, a USB data ESD device, series resistors, a USB-to-UART bridge, and a debug header.

SpeedUp-generated engineering evidence: Generated USB-C debug schematic with Type-C receptacle, separate CC resistors, data ESD protection, USB-to-UART bridge, and debug header. — This real SpeedUp-generated sheet is useful review evidence because the connector, CC resistors, VBUS entry, D+/D- protection, bridge, and debug output are visible in one place. It remains a generated first draft: the connector pinout, ESD part, resistor values, bridge implementation, footprints, and layout constraints still require verification.

This is the right role for an AI-generated schematic: make the intended circuit concrete enough to review. It is not evidence that the interface is compliant or production-ready. An engineer still checks it against the exact connector drawing, controller and bridge documentation, current Type-C requirements, layout constraints, prototype measurements, and any applicable compliance plan.

Common USB-C Schematic Mistakes

Adding a USB-C receptacle but omitting CC terminations or handling only one cable orientation.
Assuming USB-C automatically provides USB PD voltage, maximum current, or battery charging.
Using one generic connector symbol without validating hidden, duplicated, shield, or mechanical pins.
Joining D+ and D- orientation pins with long branches or routing them without an uninterrupted return path.
Selecting ESD protection by voltage alone and ignoring capacitance, clamping behavior, package, and placement.
Placing large capacitance directly on VBUS without reviewing inrush and attach behavior.
Connecting a battery charger without defining cell protection, system load sharing, charge current, or thermal limits.
Treating a visually complete schematic as proof that USB-C behavior and compliance are correct.

KiCad and PCB Layout Handoff

Before layout, open the exact connector footprint and compare it with the manufacturer drawing from both the board and mating perspectives. Confirm pad numbering, shell stakes, board edge, cutouts, courtyard, connector height, insertion clearance, and whether the footprint is intended for mid-mount, top-mount, or through-hole reinforcement.

Inspect every USB-related connection manually. An undefined VBUS source, an unintentionally open CC pin, or a missing shield connection can hide behind an otherwise tidy drawing. Unconnected pins may be intentionally unused SuperSpeed pins or a genuine omission. Record the reason for every no-connect and exception so the next reviewer can distinguish a deliberate decision from a hidden mistake.

The layout handoff should name protection placement, USB differential-pair constraints, return path, connector keepout, VBUS current and copper needs, shield strategy, test access, charger thermal copper, battery separation, and any controller configuration still owned by firmware. Schematic approval is not manufacturing approval; prototype validation, signal-integrity checks, ESD testing, thermal testing, DFM, and compliance work remain.

What SpeedUp Generates Before Engineering Review

SpeedUp can turn a product requirement into a structured first engineering draft with a block diagram, schematic hierarchy, components, and editable KiCad files. For a USB-C product, a useful prompt should state the port role, data speed, input or output power, battery and charger behavior, system load while connected, protection needs, connector constraints, test points, and expected firmware ownership.

The goal is not to skip USB-C engineering. The goal is to expose the decisions earlier so an engineer can review the CC implementation, power path, data pair, protection, charger, footprints, and layout constraints before the PCB is committed.

Product boundary: For a USB-C product, SpeedUp can translate port role, power policy, charging, data, protection, and connector requirements into structured schematic sheets and an editable KiCad first draft, then continue from the confirmed schematic into automatic PCB placement and routing for a functional prototype layout. It does not certify USB-C compliance, negotiate power in hardware, or prove signal integrity, safety, firmware, thermal behavior, or manufacturability; engineers remain responsible for reviewing the generated layout, validation, and sign-off. See the SpeedUp AI schematic generator workflow for the complete product-brief-to-editable-project path.

USB-C Circuit Design Resources

The circuit-path table above contains the focused USB protection, bridge, debug, and charging examples. Use these complementary guides when the USB-C port is part of a charger or a larger generated schematic package.

MCP73831 charger circuit checklist – charge-current programming, cell connection, thermal limits, status output, and system-load behavior.
Battery-powered sensor circuit design checklist – broader review of charging, rails, sleep current, I2C sensors, displays, and layout risks.
Schematic review checklist before PCB layout – a system-wide review path for power, interfaces, footprints, constraints, and engineering handoff.

FAQ

Does a USB-C sink need resistors on both CC pins?

A simple 5 V sink-only receptacle normally uses a separate Rd termination on CC1 and CC2 so attachment works in either cable orientation. TI’s engineering guide shows 5.1 kΩ for this basic case. Verify the latest Type-C requirements and use a controller when the port role, current handling, capacitance, data, or PD requirements exceed the simple case.

Is USB-C the same as USB Power Delivery?

No. USB-C describes the connector and Type-C connection system. USB PD adds protocol-based power negotiation over the CC connection. A product using a USB-C connector does not automatically support higher PD voltages or power levels.

Can I connect a USB-C receptacle directly to a battery charger?

Only after the Type-C sink behavior, available current, VBUS protection, inrush, and charger input limits are correctly handled. The charger must also match the cell chemistry, charge voltage, current, thermal environment, protection, and system load behavior.

How should USB 2.0 D+ and D- be connected on a Type-C receptacle?

A USB 2.0-only receptacle implementation normally combines the matching D+ orientation pins and the matching D- orientation pins near the connector, then routes one differential pair to the USB PHY. Verify the exact connector symbol and device guidance, keep branches short, and include suitable low-capacitance protection.

What must be verified before a USB-C schematic moves to layout?

Verify the Type-C role, CC connections, current assumptions, VBUS power path, USB PD behavior when used, charger limits, connector footprint, data-pair continuity, protection placement, firmware ownership, and the layout constraints handed to the PCB designer.

Start Your USB-C Hardware Project

Turn your USB-C role and power requirements into a structured, editable KiCad first draft.

Use SpeedUp to turn the product requirements into structured schematic sheets and an editable KiCad first draft for engineering review. Create a free account to begin.

Create a USB-C KiCad draft

July 21, 2026

BME280 KiCad Schematic Checklist: I2C Environmental Sensor Review

Quick Answer

SpeedUp turns a sensor-board brief into an electronics architecture, structured schematic sheets and an editable KiCad project for engineering review. For BME280, define the exact MCU, supply, interface and measurement conditions before generating that first draft.

To move a BME280 breakout-board prototype into a custom KiCad design, first decide whether the finished board will carry the complete breakout or the bare sensor. A four-wire module connection hides decisions about regulation, logic levels, pull-ups and bypass capacitors. For a bare BME280 on a shared 3.3 V I2C bus, explicitly wire both supply pins, both grounds, interface selection and address selection, then connect SDA/SCL to the chosen MCU pins. The worked ESP32 connection plan below makes those assumptions visible; placement, airflow and firmware still need their own review.

From a Breakout Board to Your Own BME280 PCB

A working breadboard prototype proves that a particular module and its wiring can communicate. It does not tell you which components belong on the next board. Start with the exact module schematic and revision, and mark which functions stay on the module and which move onto your PCB.

Decision	Keep the complete breakout	Use the bare BME280
Power input	Follow that board’s VIN specification and regulator arrangement.	Provide supplies within the sensor’s VDD and VDDIO ranges.
Logic levels	Check the module’s level-shifting circuit and pull-up rails.	Match the MCU logic domain; decide whether translation is needed.
Bus resistors	Count the resistors already fitted to every connected board.	Specify the pull-ups as part of the complete bus design.
Assembly	Provide a connector or mounting pattern for the exact module.	Assign and check the sensor’s LGA footprint, orientation and assembly requirements.

For example, Adafruit documents regulation and level shifting on its BME280 breakout. Those are properties of that board, not permissions to apply its VIN voltage directly to a bare sensor. Inspect the matching breakout schematic before reusing its connections.

BME280 KiCad Schematic Checklist

Set these decisions before drawing the sensor block. The connection tables below show how to make them explicit in a 3.3 V ESP32 example.

Decision	Record in the project
Part and assembly	Bare BME280 or exact breakout revision; symbol, footprint and orientation.
Power and logic	VDD, VDDIO, MCU logic rail and local bypassing; no assumed 5 V tolerance.
Bus configuration	I2C/SPI selection, address, GPIO allocation, bus speed and all installed pull-ups.
Operating conditions	Sampling and radio activity, power states, enclosure airflow and heat sources.
Bring-up access	Supply and bus test points, MCU programming path and expected device address.

Ready to turn your BME280 requirements into an editable KiCad draft?

Create a free account, then specify your MCU, supply, sensor interface and operating conditions. SpeedUp turns that brief into structured schematic sheets and an editable KiCad first draft. Review and confirm the schematic before continuing to automatic PCB placement and routing.

Generate my BME280 KiCad draft

The schematic does not need to solve every mechanical issue, but it should leave enough notes that the layout and enclosure teams do not bury the sensor in the wrong place.

BME280 I2C Connections to Check in KiCad

This table applies to the bare BME280, not a module header. Cross-check symbol pins against footprint pads before routing.

Pin / item	I2C connection
8 — VDD	Sensor supply: 1.71–3.6 V.
6 — VDDIO	Interface supply: 1.2–3.6 V; match the host logic domain.
1 and 7 — GND	Connect both to ground.
2 — CSB	Connect directly to VDDIO for I2C.
3 — SDI; 4 — SCK	Connect to SDA and SCL respectively, with pull-ups to VDDIO.
5 — SDO	GND selects 7-bit address 0x76; VDDIO selects 0x77. Do not float.
Supply bypass	100 nF from each supply pin to ground in Bosch’s connection diagram.
Pull-ups	Bosch gives 4.7 kΩ as a typical value; select for bus load and timing.

Source: Bosch BME280 datasheet, sections 1.1, 6.2 and 7.1–7.2. Check the top/bottom-view orientation carefully. Neither bare-chip supply is a 5 V input.

Worked Connection Plan: BME280 and ESP32-WROOM-32E

Design conditions: bare BME280, ESP32-WROOM-32E, one externally regulated 3.3 V rail, common ground, and a short on-board I2C bus initially configured for 100 kHz. This connection plan excludes a battery charger, USB power circuit and display. Adding any of those requires additional design decisions.

Net / function	BME280 connection	ESP32-WROOM-32E / board connection
`3V3`	VDD pin 8 and VDDIO pin 6; separate local 100 nF bypass capacitors.	Module 3V3 pin 2; include its own supply decoupling.
`GND`	Pins 1 and 7.	Common return with the module and input supply.
`I2C_SDA`	SDI pin 3.	GPIO21, module pad 33; configure the same GPIO in firmware.
`I2C_SCL`	SCK pin 4.	GPIO22, module pad 36; configure the same GPIO in firmware.
I2C mode	CSB pin 2 directly to VDDIO.	No SPI chip-select signal is needed in this example.
Address	SDO pin 5 to GND: 7-bit address `0x76`.	Use `0x76` in the driver configuration.
Pull-ups	One resistor from SDA to 3V3 and one from SCL to 3V3.	Start evaluation with 4.7 kΩ per line; confirm timing and bus load.

The sensor pin assignments come from Bosch’s connection table above. The MCU pad mapping comes from the ESP32-WROOM-32E module datasheet. GPIO numbers, module pad numbers and development-board header positions are different identifiers. This GPIO choice is specific to the selected module; do not copy it unchanged to an ESP32-C3 or ESP32-S3 design.

What the ESP32 development board used to provide

Moving from a development board to an ESP32 module also moves responsibility for its supply, enable/reset network, boot selection and programming connection onto your PCB. Keep these in the MCU sheet rather than treating the sensor connection table as a complete board design. Document whether programming uses a 3.3 V UART adapter and manual boot/reset buttons or a separate automatic programming circuit.

Espressif recommends a 3.3 V supply capable of at least 500 mA for ESP32, with decoupling and suitable power-up timing. Size the source for the selected module, transmit peaks and additional loads; the sensor’s small average current is not a sufficient supply budget. Check the ESP32 hardware design guidelines alongside the module datasheet. A USB-UART adapter’s voltage-reference pin should not be assumed to provide adequate board power.

What changes when you add an OLED or a battery?

Change to the example	Recheck before copying the circuit
An I2C OLED or another sensor module	Check its address, logic voltage and all fitted SDA/SCL pull-ups. Devices with different addresses can still create an unsuitable combined pull-up resistance.
Two BME280 devices	Give them distinct addresses, 0x76 and 0x77, using the SDO connection. Record both addresses in the schematic and firmware configuration.
A longer cable or faster bus	Re-evaluate bus capacitance, rise time, sink current and signal integrity. The initial 4.7 kΩ choice is not a universal value.
Battery operation	Define the battery voltage range, regulator behavior, MCU wake/transmit schedule and peripheral standby loads. Treat charging and power-path control as separate circuit blocks.
A switched sensor supply	Check whether SDA/SCL or other pins can remain driven while sensor power is off, and verify the device’s power-sequencing and unpowered-pin limits.

A concrete pull-up example: two 4.7 kΩ pull-ups connected to the same line and rail appear in parallel as 2.35 kΩ. At 3.3 V, the approximate current through that pair while the line is low is 1.4 mA, assuming a near-zero low level. That is not the average bus current or proof of a fault; it shows why adding a module changes the electrical conditions. Use the I2C pull-up calculation guide to check the assembled bus.

How to capture the migration in KiCad

Record the module-versus-bare-chip choice and the exact ESP32 variant on the first sheet.
Draw the sensor sheet using explicit supply, interface-select and address connections; assign the footprint against Bosch’s package drawing.
Use consistent 3V3, GND, I2C_SDA and I2C_SCL names across the MCU and sensor sheets. Confirm the hierarchical connections in the generated netlist.
Inspect the entire bus for duplicate pull-ups and conflicting addresses, including optional modules.
Add test access and notes for airflow, heat separation, antenna clearance and assembly. During prototype bring-up, verify the supply, boot behavior and I2C communication before assessing measurement accuracy.

Placement and Enclosure Review

Electrical connectivity and environmental measurement are separate checks. Put the sensor near the intended airflow path, away from MCU, regulator, charger and display heat. Record vent access, port clearance and assembly restrictions so those decisions survive the move from schematic to layout.

Validate the assembled board in its intended enclosure and operating states. A reading taken while Wi-Fi is transmitting or a charger is warm may reflect a different local environment from an idle, open-board test. Keep coating, adhesive and contamination away from the sensing area and follow Bosch’s handling instructions.

Example From a Real SpeedUp Project

The Temperature Humidity Sensor KiCad Project with USB-C Charging is a real SpeedUp-generated environmental sensor project. It does not use BME280; the generated sensor block uses CHT20MEMS. Use it to inspect the project structure; use the BME280-specific connection plan above for the sensor wiring.

The project is still a useful example because it shows how SpeedUp structures a sensor product around power, control/display, and environmental sensing blocks.

SpeedUp-generated engineering evidence: Top-level KiCad schematic for a generated temperature humidity sensor project, showing power, sensor, and control UI sheets. — SpeedUp-generated project evidence: The top-level schematic separates power, sensing, and control/display sections so each review area can be checked before layout.

For a BME280 version, the sensor sheet would need the BME280 symbol and footprint, I2C or SPI wiring, address pin, local decoupling, placement notes, and firmware assumptions. Use the decoupling capacitor value and placement guide to review the bypass network before layout. The review process is the same: inspect the sensor as part of the whole product, not as a disconnected breakout-board block.

SpeedUp-generated engineering evidence: Generated temperature and humidity sensor schematic sheet showing an I2C environmental sensor on a 3.3 V bus. — This real SpeedUp-generated sensor sheet uses CHT20MEMS, not BME280, but it shows the same I2C environmental-sensor review pattern: rail, bus, local decoupling, and placement assumptions.

What the published project files let you verify

The top-level KiCad sheet separates POWER, SENSOR, and CONTROL_UI, with named 3V3, I2C0_SCL, and I2C0_SDA connections crossing the sheet boundaries.
The sensor sheet connects the CHT20MEMS device to 3.3 V, ground, SCL, and SDA, and shows a local 0.1uF bypass capacitor. A BME280 implementation needs the same checks plus its interface-selection and address pins.
Download the editable KiCad project archive to inspect the sheet hierarchy and source schematic. This is evidence for the CHT20MEMS project shown here, not a BME280 reference design.

The strongest value is that the generated project is editable in KiCad. An engineer can swap the sensor choice, check the bus, review the footprint, and add layout notes before the design becomes a PCB.

What to Put in a SpeedUp Prompt for a BME280 Sensor Board

If you want a BME280-focused first draft, describe the device and the physical measurement problem, not only the part number.

Example prompt:

Design an editable KiCad first draft for an ESP32-WROOM-32E board with a bare BME280 on a short 100 kHz I2C bus. Use an externally regulated 3.3 V supply with capacity for ESP32 transmit peaks and peripheral margin. Assign GPIO21 to SDA and GPIO22 to SCL; select BME280 address 0x76. Include sensor bypass capacitors, one evaluated pair of bus pull-ups, MCU decoupling, enable/reset and boot circuitry, a clearly labelled 3.3 V UART programming interface, and supply/I2C test points. Keep USB charging, batteries and displays outside this first example. Separate the MCU and sensor sheets, provide symbol/footprint assignments and a BOM, and add sensor airflow, heat-separation and antenna-clearance notes. This is an untested first draft for engineering review.

That prompt gives the generated design enough context to produce a reviewable schematic. It still needs human validation against the Bosch documentation, the selected supply, enclosure design, firmware behavior, and layout.

Before generating the project, use the hardware requirements specification template to record the supply range, interface choice, sampling behavior, operating states, enclosure assumptions, and verification criteria that the schematic must support.

Common Mistakes

Copying a breakout VIN rating onto the bare sensor supply pins.
Confusing ESP32 GPIO numbers with module pads or development-board headers.
Leaving interface or address straps implicit because the original module provided them.
Adding a second module without recalculating the bus pull-ups.
Assuming an editable schematic or an I2C response proves measurement accuracy in the final enclosure.

What SpeedUp Generates for a BME280 Sensor Workflow

SpeedUp can help turn a product prompt into a structured KiCad schematic draft. For a BME280 environmental sensor, that means the output can include a block diagram, power tree, sensor sheet, I2C bus, display or wireless interface, BOM preview, and review notes. The schematic capture workflow explains how those requirements move into reviewable sheets and an editable engineering handoff.

After Schematic Confirmation: Automatic PCB Placement and Routing

Once you have reviewed and confirmed the schematic in SpeedUp, continue to automatic PCB placement and routing for a functional prototype PCB layout. For a BME280 sensor board, document the intended sensor location, enclosure airflow path, separation from heat sources, connector positions, and footprint requirements before this step.

Check the generated layout against those requirements, including sensor clearance, local decoupling, and access to power and I2C test points. Automatic placement and routing do not establish temperature, humidity, or pressure accuracy. Validate the assembled prototype in its intended enclosure and operating conditions; firmware integration, calibration checks, and manufacturing validation remain part of the engineering work.

Product boundary: The schematic draft and subsequent functional prototype PCB layout both require engineering review. Generating a layout does not validate sensor placement, airflow, self-heating, enclosure effects, measurement accuracy, firmware, or production performance. Engineers retain responsibility for those checks and the final design release. The CHT20MEMS example above demonstrates schematic structure; it is not evidence of a generated or tested BME280 PCB. See the SpeedUp schematic-to-PCB workflow for the full sequence.

Related SpeedUp Guides

Battery-powered sensor circuit design — extend the externally powered example with an explicit battery and operating-state budget.
ESP32 pin selection for schematic design — review GPIO, boot and peripheral assignments for the MCU sheet.

FAQ

Can I copy a BME280 module wiring diagram into a custom PCB?

Use it as a starting point only after identifying the exact module and its onboard components. Keeping the whole module requires its connector and input specifications; replacing it with the bare sensor requires you to supply the missing regulation, logic-domain decisions, pull-ups, bypassing and address/interface connections.

Can a bare BME280 connect to 5 V?

No: its specified VDD and VDDIO operating ranges stop at 3.6 V. A breakout that accepts 5 V may contain additional circuitry. Check the exact board schematic instead of transferring its VIN rating to the sensor pins.

Which ESP32 pins should I use for BME280 I2C?

This worked plan uses GPIO21 for SDA and GPIO22 for SCL on ESP32-WROOM-32E, with matching firmware configuration. Check availability and pin restrictions for your exact ESP32 variant; GPIO identifiers are not module pad numbers.

Does adding an OLED change the BME280 circuit?

It can change bus loading, pull-up resistance, supply demand and placement. Check the actual OLED module’s address, voltage and resistors before sharing the bus. Different I2C addresses do not by themselves establish electrical compatibility.

Can SpeedUp continue from the schematic to a PCB layout?

Yes. After you review and confirm the schematic, SpeedUp supports automatic PCB placement and routing to generate a functional prototype PCB layout. Review the result for sensor placement, thermal isolation, airflow and test access, then validate the assembled prototype. The historical CHT20MEMS download in this article is a separate schematic example, not a finished BME280 PCB.

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July 15, 2026

SN65HVD230 CAN Bus Schematic Checklist Before PCB Layout

Quick Answer

SpeedUp starts with product requirements for a 3.3 V CAN node using the SN65HVD230, maps logic power, controller signals, bus protection, termination, and connector pins into the electronics architecture, and delivers structured schematic sheets with an editable KiCad project for engineering review. The SpeedUp Demo: ESP32 E-Ink MQTT Display shows the same workflow with concrete engineering artifacts.

The SN65HVD230 is a 3.3 V CAN transceiver, so a good SN65HVD230 schematic is not just the IC symbol wired to CANH and CANL. Before PCB layout, review the 3.3 V supply, TXD/RXD logic connections, CANH/CANL bus pins, termination strategy, R/S slope-control or standby behavior, connector pinout, ESD protection, common-mode and fault assumptions, test points, and whether the selected part is still the best fit for a new design.

For a KiCad project, treat the CAN transceiver as an interface block between a microcontroller CAN controller and the outside bus. The schematic should show what the transceiver connects to, how the bus leaves the board, whether the node terminates the bus, how standby is controlled, and what the layout engineer must preserve. SpeedUp can help draft a reviewable KiCad schematic from a product prompt, but engineers should still verify the CAN block against the TI datasheet, the network topology, and the target product environment.

Why SN65HVD230 Schematics Need System-Level Review

Searches for sn65hvd230 schematic often return datasheets, breakout boards, module schematics, forum reviews, and reference designs. Those are useful, but they do not answer the most important product question: what kind of CAN node are you building?

A CAN transceiver circuit changes depending on:

whether the board is an end node or a middle node
whether the network already has 120 ohm termination at both ends
whether the connector is an automotive, industrial, internal harness, or lab connector
whether the MCU has a built-in CAN controller or uses a separate controller
whether the design needs low-power standby
what ESD, surge, and fault conditions the bus may see
whether the product is a prototype, field device, motor controller, sensor node, or diagnostic tool
whether a newer CAN or CAN FD transceiver is a better choice for the application

That is why the schematic should not be a floating module copied from a breakout board. It should explain the node, the bus, the control pins, and the layout constraints.

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SN65HVD230 CAN Bus Schematic Checklist

Use this checklist before moving an SN65HVD230-based CAN block into PCB layout.

Review area	What to check in the schematic	Why it matters before PCB layout
Part choice	Confirm SN65HVD230, package, availability, and whether a newer TI alternative is more appropriate.	TI lists newer related transceivers; a new design should not choose an older part blindly.
Supply rail	Verify the 3.3 V supply, local decoupling, current budget, and power-domain naming.	The transceiver depends on a stable local rail and clean return path.
MCU interface	Check TXD, RXD, logic levels, pin names, and whether the MCU actually has a CAN controller.	A CAN transceiver is not a CAN controller; it converts controller signals to the bus physical layer.
R/S pin behavior	Decide whether R/S is tied for high-speed mode, uses slope control, or is driven for standby/listen behavior.	This pin affects emissions, power mode, and whether the device can transmit.
CANH/CANL pins	Route CANH and CANL as a pair with clear names and connector mapping.	Layout must preserve the bus pair and avoid accidental swaps.
Termination	Decide whether this board needs 120 ohm termination, split termination, optional jumper termination, or no termination.	Wrong termination can break bus reliability, especially when multiple nodes are connected.
ESD and protection	Add or document TVS/ESD strategy, common-mode choke if used, and expected bus fault environment.	External CAN connectors can face real-world stress that the IC alone may not cover.
Connector and cable	Label connector pins, shield/chassis assumptions, ground reference, and harness orientation.	CAN issues often start at the connector and cable, not the IC.
Test access	Add test points for 3.3 V, ground, TXD, RXD, CANH, CANL, and optional standby/slope node.	Bring-up and bus debugging need measurable nodes.
Layout notes	Add notes for short decoupling paths, bus pair routing, connector placement, protection placement, and ground strategy.	A clean schematic still needs physical constraints for a reliable bus.

The schematic should answer the reviewer's first questions without forcing them to infer the product architecture from a tiny IC block.

Termination and Connector Review

CAN bus termination is a system decision. A single schematic block cannot decide it unless the product's position on the bus is known.

For the complete endpoint topology, two-resistor placement rule, 60-ohm powered-off resistance test, and split-termination tradeoffs, use the CAN bus termination resistor placement and testing guide.

Before layout, write down:

Is this board always one end of the bus?
Is this board sometimes plugged into an already terminated network?
Should termination be fixed, jumper-selectable, switchable, or omitted?
Does the connector include CANH, CANL, ground, shield, power, or wake signals?
Does the product need a common-mode choke, ESD array, or TVS diode near the connector?
Are CANH and CANL clearly named from IC pins to connector pins?
Are test pads available for oscilloscope probing during bring-up?

If the product may be used in multiple bus positions, a selectable termination option can be more useful than hard-wiring 120 ohms. If the product is a fixed endpoint, permanent termination may be simpler. Either way, the schematic should say why.

R/S Pin, Slope Control, and Standby

The R/S pin is one of the review points that gets lost in quick SN65HVD230 circuits. TI documents that the SN65HVD230/SN65HVD231 R/S pin can select high-speed operation, slope-controlled operation, or a low-power mode depending on how the pin is connected or driven.

In a schematic review, ask:

Is R/S tied low for high-speed operation?
Is a resistor used for slope control to reduce emissions?
Is R/S controlled by the MCU for standby or listen-only behavior?
Does firmware know which mode the hardware selects?
Is the default state safe during reset and power-up?
Does the design need wake behavior, or only normal operation?

For a field product, this should not be left as an unexplained net. Name the control signal and document the intended operating mode.

Example From a Real SpeedUp Project

The Desktop Robot ESP32 KiCad schematic project is not an SN65HVD230 CAN node. It is useful here because it shows the review workflow SpeedUp aims to create: a product prompt becomes a structured KiCad project with named sheets, visible interfaces, and blocks that can be inspected before layout.

Top-level KiCad schematic for a SpeedUp-generated desktop robot project, showing power, compute, display, sensing, and user-interface sheets. — SpeedUp-generated project evidence: The top-level schematic shows how interface blocks should live inside a product architecture instead of appearing as isolated reference circuits.

For a CAN sensor node, you would want the same structure: power input, MCU or CAN controller, SN65HVD230 transceiver, connector, protection, termination, test points, and layout notes. The generated project should make those blocks reviewable in KiCad before a board is routed.

SpeedUp-generated engineering evidence: Compute and wireless schematic sheet for the generated desktop robot project. — This real SpeedUp-generated compute sheet shows the kind of MCU-facing interface review that also applies to CAN: signal names, control assumptions, power domains, firmware-visible pins, and layout-sensitive connections.

The evidence is not that the desktop robot contains a CAN transceiver. The evidence is the workflow: structured schematic generation gives engineers a place to inspect the decisions that matter before layout.

What to Put in a SpeedUp Prompt for an SN65HVD230 CAN Node

If you want an AI-generated first draft for a CAN interface, describe the whole node, not just the transceiver part number.

Example prompt:

Design a 3.3 V CAN sensor node as an editable KiCad project. Include an MCU with CAN controller support, an SN65HVD230 CAN transceiver, CANH/CANL connector, optional selectable 120 ohm termination, ESD protection near the connector, R/S slope-control or standby wiring, 3.3 V power regulation, test points for TXD, RXD, CANH, CANL, 3.3 V, and ground, and layout notes for bus routing and protection placement. Make the design a first engineering draft for review, not a production-ready reference design.

That prompt gives the generated schematic enough context to be useful. The engineer still needs to verify the part choice, network topology, ESD strategy, termination, firmware behavior, connector pinout, layout, and compliance needs.

Common Mistakes

Treating the SN65HVD230 as a CAN controller. It is a transceiver; the design still needs a CAN controller in the MCU or a separate controller IC.
Copying a breakout-board schematic without checking whether the product is an end node, middle node, or diagnostic adapter.
Hard-wiring termination when the node may plug into an already terminated bus.
Leaving the R/S pin unexplained, especially when standby, slope control, emissions, or firmware behavior matter.
Forgetting ESD or surge protection when CANH and CANL leave the enclosure.
Swapping CANH/CANL at the connector or failing to label the harness direction.
Ignoring newer CAN transceiver options for new designs, especially if CAN FD, wider fault protection, or different IO support is required.
Moving to PCB layout without test points for CANH, CANL, TXD, RXD, ground, and the local 3.3 V rail.

What SpeedUp Generates Before Engineering Review

SpeedUp can help turn a CAN-enabled product requirement into a structured KiCad schematic draft. For an SN65HVD230 design, that means the transceiver can be drafted in context: MCU interface, bus connector, protection, termination option, R/S behavior, test access, and layout notes.

The result should be treated as a review starting point. Engineers still verify the TI datasheet, component availability, alternate transceiver options, bus topology, termination, protection, footprints, cable assumptions, firmware behavior, layout constraints, and bring-up procedure. The value is not blind automation. The value is getting from product idea to a reviewable schematic faster.

Product boundary: For an SN65HVD230 CAN node, SpeedUp can turn controller, transceiver, termination, connector, protection, and power requirements into a reviewable electronics architecture and editable KiCad first draft. It does not prove bus timing, fault survival, EMC performance, cable behavior, layout quality, firmware operation, or compliance; engineers remain responsible for those validations and release decisions. See the SpeedUp AI schematic generator workflow for the complete product-brief-to-editable-project path.

Related SpeedUp Projects and Guides

Desktop Robot ESP32 KiCad Schematic Project Generated from a Prompt – a real generated KiCad project with structured sheets and reviewable interface blocks.
What to Check Before Using an AI-Generated KiCad Schematic for PCB Layout – a downstream checklist for moving generated schematics toward layout.
Solder jumpers in KiCad schematics before layout – useful when CAN termination or operating-mode configuration may need a selectable hardware option.
KiCad Schematic Generator: From Product Prompt to Editable KiCad Project – the core SpeedUp workflow for turning product requirements into KiCad schematic drafts.
How to Review AI-Generated KiCad Schematics Before PCB Layout – a broader review process before generated circuits move downstream.

FAQ

What is SN65HVD230?

SN65HVD230 is a Texas Instruments 3.3 V CAN bus transceiver. Use the official TI SN65HVD230 product page and SN65HVD23x datasheet for current specifications, package details, operating limits, and alternative-device guidance.

Is SN65HVD230 a CAN controller?

No. SN65HVD230 is the physical-layer transceiver between a CAN controller and the differential CAN bus. Your design still needs a microcontroller with CAN support or a separate CAN controller.

Does every SN65HVD230 circuit need 120 ohm termination?

No. CAN termination depends on the bus topology. The two physical ends of a CAN bus normally need termination, but a middle node or diagnostic adapter may not. The schematic should document whether termination is fixed, selectable, or omitted.

What should I check first in an SN65HVD230 schematic?

Start with 3.3 V supply and decoupling, TXD/RXD connections, CANH/CANL connector mapping, termination, R/S pin behavior, ESD/protection, and whether the board's role on the bus is defined.

Can AI generate an SN65HVD230 CAN bus schematic?

AI can draft a first KiCad schematic block and place it in a larger product architecture, but the result still needs engineering review against the datasheet, bus topology, connector, protection strategy, firmware behavior, and PCB layout.

Start Your 3.3 V CAN Node

Turn your CAN-node requirements into a structured, editable schematic draft.

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July 15, 2026

MCP73831 Charger Circuit: Schematic Checklist Before PCB Layout

Quick Answer

SpeedUp converts product requirements for a single-cell MCP73831 Li-ion charger into an electronics architecture covering input power, charge current, battery connections, status, and thermal limits, structured schematic sheets, and an editable KiCad project for engineering review. Explore the SpeedUp Demo: 100W PD Power Bank to see this handoff in a real project.

The MCP73831 is a common single-cell Li-Ion/Li-Polymer charger IC, but an MCP73831 charger circuit still needs careful schematic review before PCB layout. Check the input source, charge-current setting, battery connector, status output, thermal limits, load-sharing assumptions, protection parts, and whether the charger is isolated from noisy system loads. A working-looking schematic can still fail if the charge current is too high for the USB input, the battery connector is ambiguous, the thermal path is weak, or the system load interferes with charge termination.

For a KiCad project, treat the MCP73831 block as part of the whole power tree, not a standalone symbol. The charger touches USB or adapter input, battery safety, system power, mechanical placement, firmware-facing status, test points, and layout constraints. SpeedUp can help draft a reviewable KiCad schematic from requirements, but engineers should still verify the charger circuit against the Microchip datasheet and the actual battery pack.

Why MCP73831 Circuits Need More Than a Copy-Paste Schematic

Many engineers search for mcp73831 circuit or mcp73831 schematic because they want a quick charger block. The part looks simple: input, battery, programming resistor, status pin, and a few passive components. That simplicity is exactly why mistakes slip through.

The charger block is usually tied to decisions outside the IC:

USB-C, Micro-USB, pin header, dock, or adapter input
battery chemistry and capacity
charge current and thermal dissipation
product load while charging
battery connector polarity and protection
status LED or MCU charge-state input
enclosure thermal behavior
test points and bring-up procedure
layout around the charger, battery node, and input capacitor

If those decisions are not visible in the schematic, the PCB layout may hide a system-level battery problem instead of solving it.

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MCP73831 Charger Circuit Checklist

Use this checklist before moving an MCP73831-based charger block into layout.

Review area	What to check in the schematic	Why it matters before PCB layout
Part variant	Confirm the exact MCP73831/MCP73832 variant, charge voltage option, package, temperature range, and availability.	Small suffix differences can change voltage target, package, or sourcing assumptions.
Input source	Label whether the charger input comes from USB, USB-C, adapter, dock, or another regulated rail.	Input current limit, connector protection, cable behavior, and upstream voltage quality affect charging.
Charge current	Check the programming resistor value and compare charge current to battery capacity, USB budget, and thermal limits.	Over-aggressive charge current can overheat the IC or exceed the input source.
Battery connector	Name battery positive/negative clearly, include polarity/keying assumptions, and check connector footprint.	Battery connector mistakes are expensive and can be unsafe.
Battery protection	Decide whether protection is inside the cell pack or must be added on the board.	The charger IC is not the whole battery-safety system.
System load path	Decide whether the product can run while charging and whether load sharing or power-path control is needed.	A system load can affect charge termination, battery behavior, and user-visible reliability.
Status output	Route STAT to an LED, MCU input, or test point with the right pullup/current-limit assumptions.	Charge-state visibility helps bring-up, firmware, and user feedback.
Thermal behavior	Estimate worst-case dissipation and give the package enough copper and airflow for the product enclosure.	Linear chargers dissipate heat; schematic choices constrain layout.
Input/output capacitors	Use datasheet-recommended capacitors and voltage ratings close to the charger pins.	The layout must support stable charging and avoid noise on battery/input nodes.
Test access	Add test points for input voltage, battery node, status, ground, and system rail where useful.	Bring-up needs measurable nodes, especially on battery-powered products.
Layout constraints	Add notes for short battery/input paths, thermal copper, connector placement, and keepouts.	Layout quality is part of the charger design, not a separate afterthought.

The goal is not to make the schematic large. The goal is to make the assumptions explicit enough that the layout engineer, firmware engineer, and reviewer can see the same power story.

Charge Current and Thermal Review

The charge-current setting deserves its own review pass. In an MCP73831 design, the charge current is not just a resistor choice; it is a product decision.

Before layout, answer these questions:

What is the actual battery capacity?
What charge rate is acceptable for this cell and product?
Can the USB or adapter source provide the chosen current?
What happens if the product is on while charging?
How hot can the charger package get in the enclosure?
Is there enough copper near the charger to spread heat?
Does the product need a lower default charge current for safety margin?

Do not pick a high charge current just because a reference schematic uses one. Check the Microchip datasheet, the battery vendor's limits, the connector/input budget, and the thermal conditions of the real device.

Load Sharing and Power-Path Questions

Many MCP73831 mistakes come from the system-load question. A simple charger circuit may be fine when the product is off during charging. It may be less fine when the product is running from the same battery node while charging.

Review these cases:

Product behavior	Schematic question	Risk if ignored
Charges only when off	Is the load disconnected or naturally inactive during charge?	User may expect operation while charging, but the circuit may not support it.
Runs while plugged in	Is there a defined power path or load-sharing arrangement?	System current can interfere with charge termination or thermal behavior.
MCU monitors charge state	Is STAT routed to a valid logic domain with safe pullup behavior?	Firmware may read unreliable or unsafe charge status.
User LED indicates charging	Is LED current appropriate and is the LED state documented?	The user may see confusing or dim status behavior.
Battery is removable	Is reverse insertion, connector keying, and exposed terminal behavior considered?	Mechanical and safety risk increases.

If the device must run while charging, do not treat the charger as a complete power-management solution by itself. Add the missing power-path design explicitly or document why it is not needed. For an integrated charger and load-sharing alternative, compare the BQ24074 charger and power-path checklist.

Example From a Real SpeedUp Project

The Desktop Robot ESP32 KiCad schematic project is not an MCP73831 charger design. It is useful here because it shows how a generated KiCad project can separate power, compute, display, sensing, and user-interface sheets so the power path can be reviewed before layout.

Power input and regulator schematic sheet from a SpeedUp-generated desktop robot KiCad project. — This real SpeedUp-generated power sheet shows the kind of schematic evidence reviewers need: named power input, regulated rails, protection assumptions, power-status signals, and clear places to ask charger or battery questions.

For an MCP73831-based design, the charger block should live in the same kind of reviewable power sheet. The reviewer should be able to see the input connector, charger IC, battery connector, charge-current programming, status output, system rail relationship, protection assumptions, and layout notes without hunting through a flat schematic.

SpeedUp-generated engineering evidence: Top-level KiCad schematic for a generated desktop robot project, showing power, compute, display, sensing, and user-interface sheets. — From the same SpeedUp project: A top-level sheet helps keep the charger block connected to the rest of the product architecture instead of treating it as an isolated reference circuit.

This is the kind of output SpeedUp is meant to accelerate: a structured first draft that can be opened, inspected, edited, and reviewed in KiCad.

What to Put in a SpeedUp Prompt for an MCP73831 Charger

If you want an AI-generated first draft for a battery-powered product, describe the charger as part of the system, not just as a part number.

Example prompt:

Design a compact single-cell Li-Ion powered sensor board as an editable KiCad project. Include an MCP73831 charger from USB-C 5 V input, a protected battery connector, a 3.3 V regulator for the MCU and sensors, charge-status indication, test points for input, battery, system rail, and status, and layout notes for thermal copper and battery/input routing. Make the design a first engineering draft for review, not a production-ready reference design.

That prompt gives the generated schematic a review target. The output should still be checked against the MCP73831 datasheet, the selected battery, connector footprint, enclosure, and manufacturing process.

Common Mistakes

Copying an MCP73831 reference circuit without checking the exact part variant and charge-voltage option.
Setting charge current without checking battery capacity, input-source budget, and thermal dissipation.
Forgetting that a product load can interfere with charging if no load-sharing or power-path decision is made.
Leaving STAT unused when the product needs user feedback, firmware awareness, or bring-up visibility.
Assuming the battery pack includes protection without verifying the actual cell or connector assembly.
Placing the charger far from the battery/input capacitors or without enough thermal copper.
Treating the charger schematic as complete while the system rail, test points, and layout notes are still undefined.

What SpeedUp Generates Before Engineering Review

SpeedUp can help turn a product requirement into a structured KiCad schematic draft. For an MCP73831 charger design, that means SpeedUp can draft the charger block in context: input source, battery node, system rail, status signal, regulator, test points, and review notes.

The engineering work does not stop there. A human reviewer still needs to verify the datasheet details, charge current, battery safety, thermal limits, footprint assignments, layout constraints, and test procedure. The best use of SpeedUp is to shorten the path from product idea to reviewable KiCad project, then let the engineer spend more time on the decisions that actually determine whether the board is safe and buildable.

Product boundary: For an MCP73831 charger product, SpeedUp can organize the input source, battery node, system rail, status signal, protection, and component context into structured schematic sheets and an editable KiCad first draft. It does not validate charge safety, cell compatibility, thermal margin, footprints, PCB layout, or bench behavior; those decisions and production sign-off remain engineering responsibilities. See the SpeedUp AI schematic generator workflow for the complete product-brief-to-editable-project path.

Related SpeedUp Projects and Guides

Desktop Robot ESP32 KiCad Schematic Project Generated from a Prompt – a real generated KiCad project with a power sheet, system rails, and reviewable schematic structure.
Battery Powered Sensor Circuit Design Checklist – a broader battery-powered design checklist that pairs naturally with charger review.
What to Check Before Using an AI-Generated KiCad Schematic for PCB Layout – downstream layout-readiness checks after the charger and power tree are reviewed.
KiCad Schematic Generator: From Product Prompt to Editable KiCad Project – the SpeedUp workflow for turning product requirements into a KiCad schematic draft.
How to Review AI-Generated KiCad Schematics Before PCB Layout – a general schematic review process before layout.

FAQ

What is MCP73831?

MCP73831 is a Microchip single-cell Li-Ion/Li-Polymer charge-management IC family. Use the official Microchip MCP73831 product page and MCP73831/MCP73832 datasheet for exact voltage options, package details, pin behavior, and application limits.

Is MCP73831 enough for a complete battery power system?

No. It can be the charger IC, but the whole system may also need input protection, battery protection, load sharing or power-path control, regulation, status indication, test points, thermal review, and layout constraints.

What should I check first in an MCP73831 schematic?

Start with the exact part variant, input source, charge-current setting, battery connector, STAT routing, and whether the product load is active while charging. Then review capacitors, protection, thermal behavior, footprints, and layout notes.

Can I use MCP73831 with USB-C?

Yes, but the USB-C input must be designed correctly. The schematic still needs the right connector assumptions, CC resistors or upstream USB-C handling as appropriate, input protection, current budget, and a clear connection from 5 V input to the charger.

Can AI generate an MCP73831 charger circuit?

AI can draft a first schematic block and place it in a larger KiCad project, but the result still needs engineering review against the datasheet, battery requirements, thermal limits, PCB layout, and test procedure.

Start Your LiPo Charger Project

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Use SpeedUp to turn the product requirements into structured schematic sheets and an editable KiCad first draft for engineering review. Create a free account to begin.

Create a charger KiCad draft

July 13, 2026