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Quick Answer

A reliable LIS2DW12 accelerometer circuit starts by separating three decisions that are easy to blur together: sensor-core power on VDD, interface power on VDDIO, and digital-bus selection on CS. For I2C, tie CS high to VDDIO, pull SDA and SCL up to that same logic rail, and set SDO/SA0 low for address 0x18 or high for 0x19. For SPI, route the clock and data pins for the intended three-wire or four-wire mode and give chip select a defined inactive state. In either mode, ground RES, connect both ground pins, place the required bypass capacitors at the supply pins, and decide whether INT1, INT2, or neither will carry wake-up and data-ready events.

SpeedUp turns wearable-device requirements that include motion sensing into an electronics architecture covering power domains, bus selection, interrupt routing, and low-power behavior, then into structured schematic sheets and an editable KiCad project for engineering review. That workflow is most useful when the prompt states the host voltage, interface, I2C address or SPI mode, interrupt behavior, motion range, sample rate, mechanical orientation, and power target instead of simply saying “add an accelerometer.” The checks below follow the current ST LIS2DW12 datasheet and use a real smart-ring schematic to show where a plausible first draft still needs system-level review.

What the LIS2DW12 Does

The LIS2DW12 is a three-axis MEMS accelerometer intended for always-on, low-power motion sensing. ST specifies selectable full-scale ranges of ±2 g, ±4 g, ±8 g, and ±16 g; output data rates from 1.6 Hz to 1600 Hz; a 32-level FIFO; and embedded motion functions such as wake-up, free-fall, orientation, and tap detection. The device communicates over I2C or SPI and comes in a 12-lead 2 × 2 × 0.7 mm LGA package. Those features make it a practical fit for wearables, asset trackers, remote controls, sensor nodes, and products that wake a larger processor only after motion is detected. If the product instead needs combined acceleration and angular-rate sensing, review the MPU6050 schematic checklist and lifecycle alternatives before selecting a current 6-axis IMU.

The low-power headline does not by itself guarantee a low-power product. Consumption depends on operating mode, data rate, bandwidth, FIFO use, interrupt configuration, and how often the host wakes to read samples. A circuit review therefore has to connect the schematic to the firmware contract. The official LIS2DW12 product page is useful for confirming the active device and headline capabilities; the datasheet and AN5038 application note contain the electrical and configuration details that should govern the design.

Design area	LIS2DW12 capability	Decision to record
Supply	VDD operates from 1.62 V to 3.6 V, with a separate VDDIO interface supply	Rail values, sequencing, decoupling, and the host logic level
Digital interface	I2C or three-/four-wire SPI	Bus mode, maximum bus rate, pull-ups or chip-select ownership, and startup state
Measurement	±2/4/8/16 g and 1.6–1600 Hz output data rate	Range, sample rate, bandwidth, noise, and power mode
Event handling	Programmable INT1 and INT2	Wake-up source, polarity, drive type, latching, and MCU pin
Sample buffering	32-level FIFO	Watermark, host wake interval, latency, and overflow behavior
Package	12-lead 2 × 2 mm LGA	Land pattern, pin-one marking, axis orientation, assembly process, and placement

Five-Minute LIS2DW12 Circuit Checklist

Check	Pass condition	Why it matters
Exact part	Symbol, footprint, BOM, and orderable code all identify LIS2DW12 or LIS2DW12TR in the LGA-12 package	A familiar accelerometer symbol is not evidence that the pinout or land pattern matches
Power domains	VDD and VDDIO are inside their limits and consistent with MCU logic	The sensor core and interface can have different supply requirements
Mode select	CS is intentionally high for I2C or controlled for SPI	An undefined mode pin can make a correct bus look dead
I2C address	SDO/SA0 selects 0x18 or 0x19 without conflicting with another device	Firmware and schematic must use the same address
Reserved pin	RES is connected to ground	This is a required connection, not a spare GPIO
Decoupling	Local capacitors are placed at VDD and VDDIO, with short returns and rail bulk reviewed	Remote capacitance does not control the local current loop as well
Interrupts	INT1/INT2 are routed or deliberately unused, with firmware behavior documented	Always-on sensing usually depends on a reliable wake signal
Orientation	Package pin one and X/Y/Z axes agree with the PCB, enclosure, and software coordinate system	A rotated sensor can look like a firmware or calibration failure

Confirm the LIS2DW12 Pin Functions

The smallest schematic mistake is often the hardest to see: a symbol looks orderly, yet one multifunction pin has been assigned according to the wrong bus mode. Confirm every pin against the package view in the datasheet, including whether the drawing is a top or bottom view. Then audit the symbol-to-footprint mapping independently. The table below uses the current ST pin definitions.

Pin	Name and role	Schematic check
1	SCL/SPC	I2C clock or SPI clock; route for the selected bus and avoid a conflicting label
2	CS	Tie high to VDDIO for I2C, or drive as active-low chip select for SPI
3	SDO/SA0	SPI data output or I2C address select; define high or low rather than leaving the address accidental
4	SDA/SDI/SDO	I2C data, four-wire SPI input, or three-wire bidirectional data
5	NC	May be left unconnected or tied as permitted by ST; never repurpose as a signal
6, 8	GND	Connect both to the local ground reference with a compact return
7	RES	Connect to ground as specified
9	VDD	Sensor-core supply; place its bypass network immediately beside the pin
10	VDDIO	Digital-interface supply; match the MCU I/O domain and I2C pull-up rail
11	INT2	Optional programmable interrupt; route, test, or mark intentionally unused
12	INT1	Optional programmable interrupt; commonly used for wake-up or data ready

CS and SDO/SA0 include weak internal pull-ups, but those do not remove the need for an intentional mode and address design. A strap close to the sensor is easier to review than an address that depends on leakage, assembly contamination, or a host pin during reset. If one PCB must support alternate addresses, use a documented resistor option or zero-ohm link and make the fitted state visible in the BOM.

Choose I2C or SPI Deliberately

I2C minimizes pins and fits a board that already carries several low-speed sensors. SPI provides a dedicated chip select, can operate at a higher serial clock, and avoids address collisions, but consumes more MCU pins and routing. Neither interface is universally better. Choose from required throughput, shared-bus capacitance, sleep-state behavior, available pins, cable or flex length, and the host software stack.

Interface choice	Required connections	Review focus
I2C, address 0x18	CS high, SDO/SA0 low, external SDA/SCL pull-ups to VDDIO	Address availability, total bus capacitance, rise time, pull-up current, and host reset behavior
I2C, address 0x19	CS high, SDO/SA0 high, external pull-ups to VDDIO	Same electrical checks, plus firmware address and fitted strap state
Four-wire SPI	CS, SPC, SDI, and SDO	Logic levels, clock rate and phase, chip-select timing, return path, and unpowered states
Three-wire SPI	CS, SPC, and bidirectional data on the supported pin	Host direction switching, bus turnaround, firmware support, and contention

For I2C, the datasheet’s application diagram shows external pull-ups; it does not make one resistor value correct for every board. Calculate the value from VDDIO, the devices’ low-level sink capability, desired bus speed, and total capacitance. A wearable with two nearby sensors may tolerate a different value from a carrier board with connectors and long traces. The I2C pull-up resistor calculation guide gives the rise-time and current checks. Also verify that another device or module has not already installed pull-ups that create an unexpectedly low parallel resistance.

Power VDD and VDDIO Correctly

VDD powers the sensing and internal logic, while VDDIO defines the digital-interface level. They may use the same rail, as they do in the smart-ring example below, but the schematic should keep their roles visible. ST specifies a 1.62 V to 3.6 V operating range for VDD. The interface supply must also remain within its documented limits and compatible with every connected host pin and pull-up.

ST’s recommended connection diagram places a 100 nF ceramic capacitor and a 10 µF bulk capacitor near VDD, plus 100 nF near VDDIO. Treat those as local current-loop components, not merely BOM entries. Put the ceramic closest to each pin, connect it to ground without a long detour, and keep switching-regulator current paths away from the sensor return. If the design relies on shared bulk capacitance elsewhere on the rail, document distance, impedance, load steps, and the reason it still meets the sensor’s local requirement. The decoupling capacitor placement guide explains why placement and return geometry matter as much as nominal value.

Power check	Pass condition	Bench evidence
VDD range	Minimum and maximum rail values, ripple, and startup stay inside the datasheet limits	Oscilloscope capture at pin 9 during startup, radio bursts, and host wake-up
VDDIO compatibility	MCU pins, I2C pull-ups, and interrupt rails share a valid logic domain	High/low levels measured at the sensor, including sleep and reset
Power sequencing	No host signal drives an unpowered interface outside the permitted state	Power-up, power-down, battery insertion, and debug-cable tests
Local bypass	100 nF capacitors are adjacent to VDD and VDDIO; VDD bulk is provided or justified	Placement screenshot, routing review, and rail transient capture
Ground return	Both ground pins and bypass returns reach a quiet local reference	Current-path markup and layout inspection
Sleep current	Measured board current matches the intended sensor mode and host state	Current profile over wake, sample, interrupt, transfer, and sleep periods

Power-state testing matters on products that switch the sensor rail while keeping the MCU alive. AN5038 describes the relationship between VDD and VDDIO and the special case in which the core supply is removed while the interface supply remains present. Do not generalize that behavior into permission for arbitrary intermediate voltages or back-powering through bus pins. Review the exact sequence, keep firmware pins in a safe state, and capture the rails at the device instead of assuming the regulator’s output tells the whole story.

Define Interrupts and the Firmware Contract

INT1 and INT2 are programmable, so the net name alone does not tell a reviewer what will happen. Write down which event reaches which pin: data ready, FIFO threshold, wake-up, free-fall, tap, orientation, or another embedded function. Then define active level, push-pull or open-drain behavior, latched or pulsed signaling, MCU wake capability, and the state during reset. The default interrupt output is not a substitute for this configuration contract.

Firmware setting	Hardware dependency	Acceptance question
Full-scale range	Mechanical shocks and desired sensitivity	Will expected motion saturate ±2 g, and is ±16 g unnecessarily noisy for the use case?
Output data rate	Power budget, motion bandwidth, and bus traffic	Does the chosen rate capture the event without waking the host too often?
Operating mode	Noise and current target	Is the selected low-power or performance mode consistent with the product requirement?
FIFO watermark	Host wake latency and memory handling	Can the host service the FIFO before overflow in its deepest sleep state?
Interrupt routing	INT1/INT2 nets and MCU pin capability	Can the selected MCU pin wake the device with the configured polarity and pulse width?
Coordinate transform	Physical X/Y/Z orientation	Does firmware report motion in product coordinates rather than package coordinates?

A useful bring-up sequence is to read the identity register first, confirm the expected I2C address or SPI response, hold the product still and inspect the gravity vector, rotate it through all axes, then validate the interrupt and FIFO configuration. Record register values alongside the schematic revision. That makes it possible to distinguish a wiring problem from a configuration problem when a later firmware build changes behavior.

PCB Layout, Orientation, and Mechanical Placement

The LIS2DW12 measures the movement of its PCB location, not an abstract enclosure center. Place it where board flex, button forces, connector insertion, speaker vibration, haptic motors, and drop impacts will not dominate the signal. Keep the package away from board edges or cutouts that bend strongly unless that behavior has been simulated and tested. In a smart ring or compact wearable, mechanical placement may be constrained, so record the tradeoff instead of letting the sensor land in the last available 2 mm square.

Layout area	Pass condition before fabrication	Evidence to retain
Footprint	Land dimensions, solder mask, paste apertures, courtyard, and pin-one marker follow the current package recommendation and assembler capability	Library audit with the datasheet package drawing
Orientation	Package axes are marked on assembly drawings and mapped to product coordinates	Annotated PCB and firmware transform
Supply loop	Bypass components and ground vias sit beside the supply pins without a shared noisy detour	Placement and return-path screenshot
Digital routing	Clock and data traces have continuous return, avoid switching nodes, and do not cross board splits	Layer-by-layer route review
Mechanical strain	Sensor is separated from high-flex regions, mounting stress, and repeated button or connector force	Board-stack drawing and mechanical test plan
Vibration sources	Motor, buzzer, speaker, and inductors are placed or characterized so their signatures are understood	Frequency-domain measurement in the final assembly
Assembly	Reflow, cleaning, handling, and package keep-out follow MEMS and assembly guidance	Manufacturer and contract-assembler process review

The STEVAL-MKI179V1 evaluation board is a useful reference for device bring-up and comparison, but it does not replace the production board’s own footprint, stackup, enclosure, or vibration review. Test the assembled product in the orientations and motions that matter to the user. A clean waveform on an evaluation board does not prove that a ring, wrist device, or tracker enclosure will behave the same way.

Example From a Real SpeedUp Smart Ring KiCad Project

The smart ring circuit design project combines an nRF52832, MAX30101 optical sensor, LIS2DW12TR accelerometer, battery charging, and a shared 1.8 V sensor rail. It is useful evidence because the accelerometer is not isolated from the rest of the product: it shares I2C with another sensor, must wake a low-power MCU, and has to fit a mechanically constrained wearable.

Generated evidence	What the draft expresses correctly	What still needs review
VDD pin 9 and VDDIO pin 10 on 1V8_SYS	The sensor and interface use one explicit 1.8 V domain compatible with a low-voltage wearable architecture	Rail tolerance, startup, radio-load transients, shutdown state, and host pin behavior
100 nF capacitors at both supply pins	Local high-frequency bypassing is represented	Physical placement and return; whether a suitable local 10 µF bulk capacitor is present on the shared rail
CS tied high	The schematic explicitly selects I2C instead of leaving the interface ambiguous	Confirm the strap reaches the same VDDIO domain and is placed clearly
SDO/SA0 connected to ground through 0 Ω	The address is intentionally set to 0x18	Firmware address, BOM fitted option, and absence of another 0x18 device
RES grounded; both ground pins shown	The required reserved and ground connections are not treated as optional	Symbol-to-footprint mapping and local ground geometry
INT1 routed as IMU_INT; INT2 unused	The architecture provides one accelerometer wake/event path	MCU pin wake capability, polarity, pulse/latch choice, boot state, and firmware register configuration
LIS2DW12 and MAX30101 share SCL/SDA	The sheet exposes the real multi-sensor bus	Locate the system pull-ups, calculate their parallel value and bus capacitance, and verify power-off behavior of both devices

This comparison shows why a generated schematic should be reviewed as a system. The visible LIS2DW12 connections cover the main mode, address, supply, reserved-pin, and interrupt decisions. The remaining questions sit across sheet boundaries or do not exist until PCB placement: total I2C pull-up resistance, rail bulk capacitance, sensor-axis orientation, mechanical strain, and whether the MCU can meet the intended wake behavior. The nRF52832 pinout and schematic guide helps review the host side of that contract.

Common LIS2DW12 Circuit Mistakes

• Copying a symbol or footprint from another LGA accelerometer because the package size looks similar.
• Leaving CS undefined and expecting the sensor to choose I2C automatically.
• Using address 0x18 in firmware while SDO/SA0 is strapped high for 0x19, or vice versa.
• Relying on weak internal pulls instead of defining the bus mode and address in the schematic.
• Pulling I2C to 3.3 V when VDDIO and the connected pins are operating at 1.8 V.
• Adding pull-ups at every sensor without calculating the lower parallel resistance and sink current.
• Placing nominal bypass values in the schematic but routing them far from the supply pins.
• Omitting local rail bulk because a larger capacitor exists near the regulator on another part of the board.
• Routing an interrupt without documenting polarity, latching, drive type, event source, and MCU wake capability.
• Rotating the footprint for routing convenience without updating the product-coordinate transform.
• Placing the MEMS sensor beside a haptic motor, board edge, button, or flex region without characterizing the resulting vibration and strain.
• Quoting a low sensor current while firmware operates at an unnecessarily high data rate and wakes the host for every sample.

What SpeedUp Generates Before Engineering Review

SpeedUp helps turn product behavior into a structured, editable KiCad first schematic draft. For an LIS2DW12 design, specify the MCU, VDD and VDDIO rails, I2C or SPI mode, I2C address or SPI wiring, full-scale range, output data rate, FIFO policy, interrupt event and polarity, coordinate orientation, and sleep-current target. Include the other devices on the bus and whether any module already supplies pull-ups. Those details let the generated architecture represent decisions that an engineer can inspect instead of hiding them behind a generic “IMU” block.

The output is not a production-ready design or a substitute for manufacturer documentation, layout review, firmware bring-up, environmental testing, or regulatory work. Use it to make requirements visible, compare connections with the latest official sources, revise the KiCad files, and create an evidence-backed review trail before fabrication. For a broader power and sensor review, use the battery-powered sensor circuit checklist alongside this component-specific guide.

Product boundary: For an LIS2DW12 motion-sensing product, SpeedUp can organize VDD and VDDIO, bus mode, address or chip-select behavior, interrupts, low-power states, orientation, and component context into structured sheets and an editable KiCad first draft. It does not validate sensor accuracy, mechanical placement, vibration behavior, firmware, PCB layout, environmental testing, compliance, or production readiness. See the SpeedUp AI schematic generator workflow for the complete product-brief-to-editable-project path.

Related LIS2DW12 and Wearable Design Resources

• Smart ring circuit design with nRF52832, MAX30101, and LIS2DW12 — the complete wearable project behind the schematic example.
• I2C pull-up resistor value calculation — calculate rise time and sink current instead of copying a resistor value.
• Decoupling capacitor value and PCB placement — review the local supply loop and effective capacitance.
• nRF52832 pinout and schematic guide — verify the MCU, wake pin, and low-power host side.
• Battery-powered sensor circuit design checklist — connect motion sensing to the whole product power budget.

FAQ

What is the LIS2DW12 I2C address?

The 7-bit I2C address is 0x18 when SDO/SA0 is low and 0x19 when it is high. Tie CS high to VDDIO to enable I2C, record the selected address in the schematic and BOM, and use the same value in firmware.

Does the LIS2DW12 need external I2C pull-up resistors?

Yes. In I2C mode, SDA and SCL need external pull-ups to VDDIO. Choose the resistance from bus voltage, total capacitance, required rise time, and device sink-current limits. If several boards or sensors install pull-ups, calculate their parallel value.

Should I use I2C or SPI for the LIS2DW12?

Use I2C when pin count and sharing a short sensor bus matter most. Use SPI when dedicated device selection, higher serial-clock capability, address independence, or the host architecture favors it. Check actual sample throughput, bus length, power states, firmware support, and available MCU pins rather than selecting from interface speed alone.

What is the difference between VDD and VDDIO?

VDD powers the sensor core; VDDIO defines the digital-interface level. They can share one compatible rail, but should remain separately named and bypassed so the design clearly shows their roles. Pull I2C up to VDDIO, and verify sequencing and unpowered-pin behavior when either domain can switch.

Can I rotate the LIS2DW12 footprint on the PCB?

The device can be placed in a rotated orientation if the footprint mapping remains correct, but the physical X/Y/Z axes rotate with it. Mark the orientation on the PCB and assembly documentation, update the firmware coordinate transform, and validate gravity and motion in the finished enclosure.

Start Your LIS2DW12 Sensor Project

Engineering note: This checklist is based on the ST LIS2DW12 datasheet, AN5038, the official product page, and the STEVAL-MKI179V1 reference available at the time of writing. Confirm the exact orderable part, current document revisions, operating limits, land pattern, and application requirements before fabrication.

Quick Answer

A correct BQ24074 charger schematic has three power nodes with different jobs: IN receives the external source, BAT connects to one Li-ion or Li-polymer cell, and OUT powers the system load. Do not join BAT and OUT as if the IC were a simple linear charger. The integrated power path gives the system priority, reduces battery charge current when the input limit is reached, and lets the battery supplement the load when the source cannot supply a peak.

SpeedUp turns BQ24074 product requirements for input power, cell limits, system load, charge controls, status, and thermal constraints into an electronics architecture, structured schematic sheets, component context, and an editable KiCad project for engineering review.

Before PCB layout, explicitly choose the EN1/EN2 input-current mode, calculate ILIM, ISET, and the BQ24074-specific ITERM resistor, define CE, TS, and TMR, and decide whether firmware needs PGOOD and CHG. Place the IN, BAT, and OUT capacitors at their pins, connect both VSS and the exposed thermal pad, and run the worst-case dissipation calculation with a discharged battery and the system load active. The detailed limits and formulas below follow the current TI BQ24074 family datasheet, with the BQ24074 column and functions kept separate from the other BQ2407x variants.

What the BQ24074 Does

The BQ24074 is a standalone single-cell linear charger with dynamic power-path management. It regulates the battery to 4.2 V, supports programmable charge current up to 1.5 A, provides a resistor-programmable input-current limit, and exposes a 4.4 V regulated system output while a valid input source is present. Its input overvoltage protection threshold is 10.5 V. That threshold is a protection boundary, not permission to choose any supply below it without checking the recommended operating conditions and thermal loss.

The important architectural advantage is that the product can run from OUT while the cell charges at BAT. If the system needs more current, charging slows before the load is starved. If the source still cannot support the load, the battery can supplement it. When external power disappears, the battery remains connected to the system through the internal path. This is different from a charger such as the MCP73831, where the system-load connection requires a separate architectural decision.

Node or function	BQ24074 role	Design decision
IN	Receives USB or adapter power and enforces the selected input-current limit	Source voltage, cable drop, connector rating, inrush, protection, and available current
BAT	Charges one 4.2 V Li-ion or Li-polymer cell and draws supplement current when needed	Cell chemistry, capacity, maximum charge current, pack protection, connector, and temperature sensing
OUT	Powers the system, regulated to 4.4 V from a valid input or connected to the battery when appropriate	Downstream regulator range, peak load, brownout behavior, and capacitance
Power path	Shares input current between the system and battery; system load receives priority	Budget input limit against worst-case system current, not charge current alone
Linear charging	Dissipates the voltage difference across internal pass devices	Check junction temperature, copper area, airflow, enclosure, and charge-current derating

Five-Minute BQ24074 Schematic Checklist

Check	Pass condition	Why it matters
Exact variant	The symbol, footprint, BOM, and pin 15 all identify BQ24074; pin 15 is ITERM	Other family members assign pin 15 to different functions
Three-node topology	The source reaches IN, the cell reaches BAT, and the product rail starts at OUT	Shorting BAT to OUT defeats the intended power path
Input mode	EN1 and EN2 are driven to a documented 100 mA, 500 mA, external-ILIM, or standby state	These pins determine how much current can enter the product
Program resistors	ILIM, ISET, and ITERM values are calculated from source, cell, system load, and termination requirements	A plausible resistor value can still violate the source or cell rating
Control pins	CE, TS, and TMR each have an intentional state; PGOOD/CHG are used or deliberately omitted	Floating or misunderstood controls create silent charge and safety failures
Capacitors	Local IN, BAT, and OUT ceramics meet the datasheet ranges after DC-bias derating	Nominal capacitance on the BOM is not the in-circuit capacitance
Thermal path	The exposed pad and VSS are grounded, with copper and thermal vias sized from a dissipation calculation	Thermal regulation may reduce charge current far below the programmed value
Load cases	Startup, discharged-cell charging, no battery, input removal, weak source, full battery, and peak system load are documented	Power-path failures usually appear at transitions, not at nominal steady state

Confirm the BQ24074 Pin Functions

BQ2407x is a family, not one interchangeable pin definition. The BQ24074 uses a 16-pin 3 × 3 mm QFN with an exposed thermal pad, and its pin 15 is the adjustable termination-current input. A reference schematic for BQ24072, BQ24073, BQ24075, or BQ24079 may show a different function in that position. Confirm the orderable part before importing a symbol or copying a family drawing.

Pin	Function	Schematic check
1	TS	Connect the supported 10 kΩ NTC network, or a fixed 10 kΩ resistor to VSS only when temperature qualification is intentionally not used
2, 3	BAT	Join both pins to the protected cell positive node and place 4.7–47 µF locally
4	CE	Active-low charge enable; never leave its ownership ambiguous
5, 6	EN2, EN1	Select input-current mode with defined logic; do not rely on an unconnected pin
7, 9	PGOOD, CHG	Open-drain outputs; add a compatible pull-up or LED path if used
8	VSS	Connect to ground even though the exposed pad is also grounded
10, 11	OUT	Join both pins to the system rail and place 4.7–47 µF locally
12, 13	ILIM, IN	Program the external input limit when selected; bypass IN with 1–10 µF
14, 15, 16	TMR, ITERM, ISET	Set safety time, termination threshold, and fast-charge current from explicit requirements
Exposed pad	Thermal pad / VSS potential	Solder to grounded copper with thermal vias; do not omit the separate pin-8 ground connection

Choose EN1 and EN2 Before Calculating Resistors

EN1 and EN2 select the input-current policy. With EN2=0 and EN1=0, the limit is 100 mA. With EN2=0 and EN1=1, it is 500 mA. With EN2=1 and EN1=0, the resistor on ILIM sets the limit. Driving both high enters standby or USB suspend mode. Treat that table as a power contract: the chosen state must match what the connector and upstream source have actually granted.

A USB-C receptacle does not automatically authorize 1.5 A merely because the charger can accept it. A sink using only the default USB Type-C current advertisement must detect the source’s advertised current, and legacy USB behavior may require a different policy. Keep the Type-C configuration, CC resistors, ESD protection, source capability, cable loss, and BQ24074 mode in one review. The USB-C schematic checklist covers the connector-side decisions.

Program ILIM, ISET, and ITERM

The external-mode input limit uses IIN_MAX = KILIM / RILIM. TI’s worked example uses a typical KILIM of 1550 AΩ. Fast-charge current uses ICHG = KISET / RISET, with a typical KISET of 890 AΩ. These typical factors are useful for selecting a nominal resistor, but the minimum and maximum factors in the electrical table determine the real production range. Check both ends against the source, battery, connector, and thermal limits.

The BQ24074 termination threshold is separately adjustable. Outside USB100 mode, the typical relation is ITERM = 0.03 × RITERM / RISET. In USB100 mode it becomes ITERM = 0.01 × RITERM / RISET, one third of the other-mode nominal value. Leaving ITERM open selects the internal default near 10% of fast-charge current. Termination detection is suspended while thermal regulation, dynamic power-path management, or input-voltage regulation is reducing charge current, so a bench test must record which loop is active before declaring that termination is broken.

Requirement	Nominal calculation	Review questions
800 mA fast charge	RISET ≈ 890 / 0.8 = 1.11 kΩ; TI selects 1.13 kΩ	Can the cell accept 0.8 A across temperature, and can the PCB dissipate the heat?
1.3 A input limit	RILIM ≈ 1550 / 1.3 = 1.19 kΩ; TI selects 1.18 kΩ	Has the source granted this current, including system load plus charging?
110 mA termination with 1.13 kΩ ISET resistor	RITERM ≈ 0.110 × 1.13 / 0.03 = 4.14 kΩ; TI selects 4.12 kΩ	Does the cell vendor allow this termination threshold, and is the mode USB100?
6.25-hour fast-charge timer	TI’s typical timer factor gives about 46.8 kΩ; the example selects 46.4 kΩ	Do cell capacity, precharge, source sharing, and derating make this duration appropriate?

Do not set ISET equal to the input limit. The current entering IN feeds both the system and the battery. If ILIM is 500 mA and the product consumes 300 mA, only the remaining current—minus conversion and quiescent effects—is available for charging. Conversely, a 300 mA ISET resistor does not stop a larger system load from drawing through OUT if the input policy allows it.

Understand the Power Path Before Sizing the Load

With a valid source, the BQ24074 regulates OUT and gives the system load priority. As total input current reaches the selected limit, the charger reduces battery current. If OUT falls toward the dynamic power-path threshold, charge current is reduced further. If the load still demands more, the battery supplement path contributes current. With the input removed or outside its usable range, the battery supplies OUT.

This behavior protects system uptime, but it can hide an undersized source. A product may appear to run correctly while slowly discharging the battery even though a cable is connected. Validate at minimum: a discharged cell plus startup load, a full cell plus peak load, battery absent, source inserted and removed under load, a current-limited or high-resistance source, and the downstream converter’s highest input current. Record VIN, VOUT, VBAT, input current, battery current, charge status, and board temperature together.

Review TS, TMR, CE, PGOOD, and CHG

TS monitors a supported 10 kΩ NTC thermistor. For a battery pack with an accessible thermistor, place the sensing network so it measures cell temperature rather than charger-board temperature. If the application deliberately does not use temperature qualification, TI specifies a fixed 10 kΩ resistor from TS to VSS to maintain a valid level. That substitution makes the charger operational; it does not make a product safe across all battery temperatures.

TMR controls the precharge and fast-charge safety timers. Leaving it open selects the internal defaults: a typical 30-minute precharge timer and 5-hour fast-charge timer. A resistor from 18 kΩ to 72 kΩ programs the duration. Grounding TMR disables the safety timers, so it should not be used as a casual way to avoid timeout during debugging. Understand why charging takes longer—system-load sharing, thermal regulation, a weak source, an oversized cell, or a damaged pack—before changing a safety boundary.

CE is active low and should be controlled or strapped deliberately. PGOOD and CHG are open-drain outputs. If the product uses them, provide pull-ups or LED paths within the datasheet limits and choose a rail that remains logically valid in every relevant power state. If they are omitted, document how firmware or the user will distinguish input present, charging, charge complete, a thermal pause, and a source fault.

Capacitors, USB-C Input, and Protection

TI specifies 1–10 µF from IN to VSS and 4.7–47 µF on both BAT and OUT. Use the capacitance after voltage, temperature, tolerance, and aging derating—not the label printed on the reel. Place each capacitor against its associated pins with a compact return. Large system capacitance belongs downstream of a deliberately reviewed path; adding it directly at the connector can create inrush that the charger input limit cannot control before the internal path is active.

The BQ24074 includes input overvoltage protection, but it is not a replacement for the connector’s complete protection strategy. Review ESD and transient exposure, reverse or miswired supplies, cable hot-plug behavior, ground return, fuse or current protection, and the voltage ratings of every component tied to VBUS. The charger’s absolute-maximum survival and OVP response do not guarantee that a USB-C TVS, capacitor, or downstream part survives the same event.

Thermal and PCB Layout Checklist

A linear power path turns voltage drop into heat. TI gives the charging dissipation relationship as the loss from IN to OUT for system plus battery current, plus the loss from OUT to BAT for battery current. The worst case is often near the beginning of fast charge when the cell voltage is low, especially if the system is also drawing current. Calculate that point with maximum input voltage, realistic low-battery voltage, maximum ambient temperature, and the actual load—not only the nominal 5 V, room-temperature case.

Layout area	Pass condition before fabrication	Evidence to retain
IN loop	Input capacitor is next to IN/VSS; connector-to-charger trace and ground return support the selected current	Annotated placement and trace-width calculation
OUT loop	Output capacitor is next to pins 10/11; the system path does not detour through a thin signal return	Current-path highlight for startup and peak load
BAT loop	Both BAT pins join the local capacitor and protected cell path with low resistance	Charge and supplement current-path highlight
Ground	Small-signal programming returns stay quiet while high-current charge and discharge returns meet at a controlled point	Ground-current map, not only a filled-plane screenshot
Thermal pad	Pad is soldered to ground copper with multiple vias; pin 8 remains grounded separately	Footprint audit, paste plan, via pattern, and copper-area estimate
Hot neighbors	Charger is separated from the cell thermistor, sensitive analog nodes, and other hot regulators	Thermal placement review and enclosure test plan
Measurements	Test access exists for IN, OUT, BAT, ground, status, and current measurements	Bring-up map and acceptance limits

Thermal regulation is protection, not a nominal operating target. If the device repeatedly reduces charge current in the expected enclosure and ambient range, improve the copper and airflow, reduce input voltage or charge current, lower system load during charging, or choose a switching charger. TI’s BQ2407x EVM user guide provides a useful physical reference, but the final board still needs its own measured thermal result.

Example From a Real SpeedUp BQ24074 KiCad Project

The temperature and humidity sensor KiCad project uses a BQ24074RGTR between a USB-C input, a single-cell battery connector, and a downstream 3.3 V converter. This is more useful than an isolated charger symbol because it exposes the real product tradeoffs: USB-C protection, source current, system load, battery supplement behavior, status visibility, and the regulator that consumes OUT.

Generated evidence	What the draft expresses	What must be confirmed or improved
BQ24074RGTR in a 16-pin exposed-pad footprint	The BOM and symbol identify the ITERM-equipped family variant	Verify the land pattern, pin-one orientation, thermal vias, paste pattern, and symbol-to-footprint mapping against the current package drawing
EN2 high, EN1 low, CE low	The intended operating state is external-ILIM mode with charging enabled	Confirm that VBUS is a valid logic source through every plug, unplug, and fault transition
3.09 kΩ on ILIM	Using the typical factor, the nominal input limit is about 502 mA	Check factor tolerance, source authorization, system peak load, and whether 500 mA leaves enough current for charging
3 kΩ on ISET and 3 kΩ on ITERM	Typical nominal values are about 297 mA fast charge and 30 mA termination outside USB100 mode	Validate against the exact cell, resistor tolerance, programming-factor range, and the selected input mode
10 kΩ from TS to ground; TMR open	The draft uses the fixed-resistor TS option and the default safety timers	Decide whether the product must sense the pack thermistor and whether the default 30-minute/5-hour timing fits the cell and load sharing
PGOOD and CHG unconnected	The charger can operate without status outputs	Decide how firmware and the user diagnose source present, charging, completion, or a paused/fault condition
10 µF local capacitors at battery and output	The expected energy-storage parts are present	Apply DC-bias derating and enforce short placement and return constraints on the PCB

The example also illustrates why the resistor values must be reviewed together. A nominal 502 mA input limit and 297 mA fast-charge current can coexist when the system load remains modest. If the downstream load rises toward the input limit, the power path will reduce battery current, and the user may see a much longer charge time than the 297 mA setting suggests. Start with the complete battery-powered sensor design checklist when the charger is only one part of a sleep, peak-current, runtime, and regulator budget.

Common BQ24074 Schematic Mistakes

• Copying the pin-15 behavior from another BQ2407x variant instead of using BQ24074 ITERM.
• Connecting the system directly to BAT and leaving OUT unused, which discards the intended load-priority power path.
• Choosing ISET from desired charge time without checking the cell rating, source limit, system load, and heat.
• Assuming a USB-C connector grants the externally programmed input current without reviewing the CC and source policy.
• Leaving EN1, EN2, or CE without a defined state during reset and power transitions.
• Grounding TMR to silence timeouts without understanding that this disables the safety timers.
• Using a fixed resistor on TS while claiming that the charger protects against unsafe cell temperature.
• Expecting charge termination while DPPM, thermal regulation, or input-voltage regulation is actively reducing current.
• Connecting only the exposed pad and omitting the required VSS pin connection.
• Programming a high current on a small board, then treating thermal charge-current reduction as a defective IC.

What SpeedUp Generates Before Engineering Review

SpeedUp helps turn product requirements into a structured, editable KiCad first schematic draft. For a BQ24074 product, the useful prompt is not “add a battery charger.” State the input connector and source policy, cell capacity and allowed charge current, system peak and sleep loads, downstream rail, temperature-sensing choice, charge indicators, safety-timer requirement, test points, and mechanical constraints. That gives the generated project enough structure to expose the three-node power path and the design decisions that still need engineering review.

The real project above shows the intended workflow: generate the complete power sheet, inspect the named nets and component values, compare every critical connection with manufacturer documentation, and revise the editable KiCad files before layout. If the product only needs a simpler charger without load-priority power routing, compare the architecture with the MCP73831 charger circuit checklist. If it needs state-of-charge estimation, add a separate gauge strategy using the MAX17048 fuel-gauge circuit guide.

Product boundary: For a BQ24074 power-path product, SpeedUp can turn input-source policy, cell limits, system load, charger controls, status, thermal constraints, and downstream rails into a structured electronics architecture and editable KiCad first draft. It does not approve battery safety, resistor calculations, thermal margin, USB-C current policy, footprints, PCB layout, bench behavior, or production readiness; engineers remain responsible for validation and release. See the SpeedUp AI schematic generator workflow for the complete product-brief-to-editable-project path.

Related Battery and Power-Path Resources

• Temperature and humidity sensor KiCad project — the full product context for the BQ24074 example.
• Battery-powered sensor circuit checklist — runtime, peaks, sleep, charging, and regulator decisions.
• MCP73831 charger circuit checklist — a simpler single-cell charger architecture.
• USB-C schematic checklist — CC, VBUS, ESD, and connector review.
• MAX17048 fuel-gauge circuit checklist — state-of-charge measurement beside the charger.

FAQ

What is the difference between BAT and OUT on the BQ24074?

BAT connects to the single cell. OUT powers the system. With a valid source, the charger regulates the system output and shares input current between the load and battery. With no usable input, the battery supplies OUT through the internal path. They should not be treated as duplicate pins.

How do I set BQ24074 charge current?

Use the resistor from ISET to VSS. The nominal relation is ICHG = KISET / RISET, with a typical factor of 890 AΩ. Select the nominal resistor, then use the datasheet’s factor range and resistor tolerance to check minimum and maximum current. The actual battery current can be lower when the input limit, system load, DPPM, or thermal regulation takes priority.

What does a 3.09 kΩ ILIM resistor set?

In external-ILIM mode, the typical 1550 AΩ factor gives approximately 1550 / 3090 = 0.502 A. That is the total input-current limit for system load plus charging, not a guaranteed 502 mA battery charge current. Production limits must use the electrical-table factor range.

Can I leave TMR open?

Yes. An open TMR selects the internal default timers, typically 30 minutes for precharge and 5 hours for fast charge. A resistor programs different durations. Connecting TMR to ground disables the safety timers and requires a deliberate safety justification.

Does the BQ24074 need an NTC thermistor?

The TS input is designed for a supported 10 kΩ NTC network. TI allows a fixed 10 kΩ resistor to ground when the TS function is not used. That keeps the input valid but removes cell-temperature qualification from the charger, so the overall product must still meet the battery’s safety requirements.

Is the BQ24074 a switching charger?

No. It is a linear charger and power-path device. That reduces external component count but makes heat proportional to voltage drop and current. If the expected board cannot dissipate the loss without routine thermal regulation, reduce the electrical stress or evaluate a switching-charger architecture.

Start Your BQ24074 Power-Path Project

Bring the source, cell, load, rail, thermal, status, and safety requirements together before choosing the three programming resistors. A complete first draft makes the weak-source, hot-board, slow-charge, and missing-status problems visible while changes are still inexpensive.

Engineering note: component limits, battery safety requirements, USB-C behavior, thermal performance, and PCB implementation must be verified for the exact product. Use the current TI BQ24074 product documentation and the exact battery manufacturer’s specifications as the final authority.

Quick Answer

SpeedUp uses product requirements for a single-cell MAX17048 fuel-gauge interface to shape an electronics architecture around battery sensing, I2C, alerts, bypassing, and charger-protection boundaries, then generates structured schematic sheets and an editable KiCad project for engineering review. See the SpeedUp Demo: 100W PD Power Bank for a live example of the prompt-to-project handoff.

A reliable MAX17048 fuel gauge circuit starts with one architectural fact: this IC estimates the state of charge of a single Li-ion or LiPo cell, but it is not a battery charger or protection circuit. Connect the MAX17048 supply and voltage-sense path to the cell as shown in the manufacturer’s 1-cell application circuit, place the required 0.1 µF bypass capacitor directly between VDD and GND, connect CTG and GND correctly, and provide pull-ups for the I2C bus. If ALRT is used, treat it as an open-drain active-low interrupt. If hardware quick-start is not deliberately required, connect QSTRT to ground.

The fixed 7-bit I2C address is 0x36. Some documentation shows 0x6C for write and 0x6D for read; those are the address bytes after the read/write bit is included, not different devices. Before PCB layout, also verify the exact TDFN or WLP package, battery model assumptions, pull-up rail, alert ownership, firmware register handling, and the physical placement of the bypass and sense return. The checklist below follows the current Analog Devices MAX17048 product documentation and applies it to a real SpeedUp-generated KiCad first schematic draft.

What the MAX17048 Does—and Does Not Do

The MAX17048 is a ModelGauge fuel-gauge IC for one Li-ion cell. It uses cell-voltage behavior and a battery model to estimate relative state of charge without a current-sense resistor. The device reports cell voltage, state of charge, and charge or discharge rate over I2C. It can also generate alerts for low state of charge, state-of-charge changes, battery voltage thresholds, and reset events.

That simplicity is useful in small wearables, recorders, sensors, and portable products, but it creates an easy misconception: the MAX17048 does not charge the cell, disconnect an unsafe cell, limit charge current, or replace pack protection. A complete battery-powered product still needs a charger, protection strategy, power-path decision, and regulators sized for the load. The fuel gauge observes the cell and informs firmware; it does not make the rest of the power tree safe.

Design question	MAX17048 role	Separate product decision
How much charge remains?	Estimates relative state of charge with ModelGauge	Define the battery model, empty voltage, temperature compensation, and user-facing percentage behavior
What is the cell voltage?	Measures the 1-cell battery through the MAX17048 voltage-sense path	Decide where the gauge sits relative to protection, power-path switches, and noisy loads
How is the battery charged?	Not handled by the fuel gauge	Select and validate the charger, charge current, input source, thermal limits, and charge termination
What happens during a fault?	Can report configured alert conditions	Provide battery protection, safe shutdown, fault handling, and any required load disconnect
How does the MCU read it?	I2C slave, up to 400 kHz	Choose the pull-up rail and values, interrupt strategy, polling cadence, and recovery behavior

MAX17048 Pin and Connection Checklist

The MAX17048 is available in an 8-pin 2 × 2 mm TDFN package and a 0.9 × 1.7 mm 8-bump WLP. The functions are the same, but the physical numbering and assembly risk differ. Confirm the orderable part, symbol, footprint, top-view convention, and pad orientation as one package decision. Do not place a WLP footprint under a TDFN symbol simply because both expose eight functions.

Function	TDFN / WLP assignment	Schematic check
CTG	Pin 1 / bump A1	Connect to ground as required by the datasheet; do not leave it floating
CELL	Pin 2 / bump A2	Do not treat this as the MAX17048 measurement input; the datasheet identifies it as not internally connected on MAX17048 and as the sense input on MAX17049
VDD	Pin 3 / bump A3	For MAX17048, connect to the positive cell terminal and use it as the supply and voltage-sense input; bypass locally with 0.1 µF
GND	Pin 4 / bump A4	Connect to the negative cell terminal with a short, quiet return; connect the TDFN exposed pad to ground
ALRT	Pin 5 / bump B4	Optional open-drain active-low output; add a compatible pull-up if used and route to an MCU interrupt only with a defined service strategy
QSTRT	Pin 6 / bump B3	Connect to ground when unused; only drive it with an intentional rising edge for hardware quick-start
SCL	Pin 7 / bump B2	Connect to the I2C clock and verify the bus pull-up, voltage, frequency, and powered-off behavior
SDA	Pin 8 / bump B1	Open-drain bidirectional I2C data; provide a pull-up and confirm the shared bus capacitance

The important MAX17048/MAX17049 distinction is easy to miss. On MAX17048, VDD is both the power input and the voltage-sense input for the single cell. The CELL function becomes relevant to the two-cell MAX17049. If a generic library symbol shows both pins as active battery-sense inputs, annotate the chosen variant so a later reviewer does not copy the wrong two-cell topology.

Connect the Battery, Bypass, and Ground Before the Digital Pins

For a 1-cell MAX17048 design, begin with the battery path rather than the I2C connector. The datasheet specifies a 2.5 V to 4.5 V operating supply range and shows VDD powered directly from the battery. Place a 0.1 µF ceramic capacitor close to VDD and GND. The connection should not detour through long traces, high-current switch nodes, or a ground path shared with charger or regulator pulses.

The gauge may be placed on the pack side or system side, but that choice must match the product’s protection and removable-battery behavior. Ask what remains powered when the system load switch opens, whether the MCU can still communicate with the gauge, where battery insertion is detected, and whether the gauge sees the same cell terminals that define the product’s usable energy. A schematic net called VBAT is not enough evidence; trace the actual connection through connectors, protection FETs, charger power-path pins, fuses, and ship-mode switches.

Keep the gauge’s ground reference quiet because voltage error becomes state-of-charge error. The MAX17048 avoids a current-sense resistor, but it still measures a cell whose terminal voltage moves with load, temperature, age, and impedance. That is why a single voltage reading cannot be translated directly into battery percentage and why layout and battery modeling both matter.

Design the I2C Bus Around Address 0x36

The MAX17048 operates as an I2C slave at speeds up to 400 kHz. Its 7-bit address is 0x36. If a driver expects a 7-bit address, pass 0x36. The values 0x6C and 0x6D are the write and read address bytes with the read/write bit already appended. Shifting 0x6C again is a common reason a board appears to have no fuel gauge at all.

Both bus lines need pull-ups supplied by the system. Size them for the MCU rail, bus capacitance, target frequency, and total parallel resistance already present on other boards or sensors. If the fuel gauge remains attached to the battery while the MCU rail turns off, also check back-power paths and the logic levels on SDA, SCL, and ALRT. The I2C pull-up resistor guide provides a calculation workflow instead of relying on a default 4.7 kΩ value.

MAX17048 registers are generally read as two bytes, most-significant byte first. A useful bring-up sequence is to confirm the device version, read VCELL at 0x02, read SOC at 0x04, inspect CONFIG at 0x0C, and check STATUS at 0x1A. Read both bytes in the same transaction where required, log the raw values, and only then apply the driver’s scaling. This separates bus, byte-order, and interpretation problems.

Use ALRT and QSTRT Deliberately

ALRT is an open-drain active-low output. It can flag low state of charge, a 1% state-of-charge change, voltage-high or voltage-low conditions, and reset-related events. If firmware uses it, connect it to a compatible always-defined pull-up rail and MCU interrupt, then document how the handler identifies and clears the source. If several power ICs share one interrupt net, every output on the net must support that wired-OR arrangement and firmware must query each device.

QSTRT is not a normal enable input. A rising edge restarts the fuel-gauge calculation in a way similar to initial power-up. The manufacturer recommends connecting it to ground when unused. Quick-start can help when a noisy power-up corrupts the initial estimate, but it should be used only under the documented battery conditions. Triggering it repeatedly under load can make the displayed percentage less trustworthy, not more accurate.

Plan Battery Modeling and Firmware Before Layout

The MAX17048 includes a default battery model that can work for some Li-ion cells, but a polished product should not assume that every pouch cell has the same discharge curve. Define the actual cell, load profile, empty voltage, temperature range, charger behavior, and brownout point. Then compare reported state of charge with measured usable runtime under realistic dynamic loads—not only a slow bench discharge.

Temperature compensation is performed through the host. The datasheet recommends measuring battery temperature periodically and updating the RCOMP parameter, with a once-per-minute cadence given for best performance. Decide where that temperature comes from and whether it represents the cell rather than a warm MCU or charger. Also decide how firmware filters percentage changes, handles battery insertion, clears alerts, detects reset, and stores any model configuration that must be reloaded.

Review area	Pass condition before PCB layout	Evidence to retain
Part and package	Exact MAX17048 order code, TDFN or WLP symbol, footprint, bump orientation, and assembly process agree	Manufacturer package drawing and footprint audit
Battery architecture	Gauge location relative to cell, protection, charger, ship mode, and load switch is explicit	Power-state diagram and battery insertion/removal behavior
VDD and bypass	VDD reaches the cell correctly and the 0.1 µF capacitor has a short local return	Annotated placement constraint
I2C	Address convention, pull-up voltage, effective resistance, bus capacitance, and off-state leakage are checked	Bus calculation and shared-device list
ALRT	Pull-up, interrupt polarity, shared-net compatibility, alert masks, and clear sequence are defined	Firmware interrupt flow and power-domain table
QSTRT	Grounded when unused or driven only by an intentional reviewed reset signal	Net ownership and quick-start test case
Battery model	Cell, empty voltage, load, temperature, and expected accuracy have been validated	Cell data, discharge tests, and model settings
Bring-up	Firmware can verify address, byte order, raw voltage, state of charge, status, alerts, and reset recovery	Register log and acceptance limits

Example From a Real SpeedUp MAX17048 KiCad Project

The magnetic AI microphone KiCad project includes a MAX17048X+T10 fuel gauge in the same power sheet as a 1-cell charger, system load switch, and 1.8 V buck regulator. This is a useful product-level example because the gauge is not floating in a tutorial circuit: it must coexist with charging, ship mode, BLE/audio loads, I2C, interrupts, and low-power firmware.

Generated evidence	What looks useful	What must be corrected or confirmed
MAX17048X+T10 with WLP-style 8-bump footprint	The BOM names an exact orderable variant and the footprint dimensions reflect a small 2 × 4 bump package	Verify the official bump map, orientation, land geometry, mask rules, assembly capability, and footprint-to-symbol mapping
0.1 µF capacitor on the fuel-gauge supply net	The expected local bypass component is present	Constrain it physically close to VDD and GND and keep the sense return out of high-current paths
Named I2C and interrupt nets	PMIC_I2C_SCL, PMIC_I2C_SDA, and PMIC_INT_N make firmware ownership reviewable	Find the actual pull-ups, calculate the effective values, confirm the rail, and verify every device sharing PMIC_INT_N is open-drain
VDD, CELL, and QSTRT converge on the displayed fuel-gauge sense network	The draft exposes the intended battery relationship instead of hiding it in a generic block	Separate the required functions: MAX17048 VDD goes to the cell, CELL is not the MAX17048 sense input, and unused QSTRT must go to ground rather than remain tied high
Fuel gauge placed beside charger and system rail	The product power architecture can be reviewed on one sheet	Confirm gauge location, charger interaction, ship-mode behavior, removable-battery behavior, and MCU access in every power state

The most important issue is the QSTRT connection. In the generated first schematic draft, QSTRT appears to join the same vertical network as the battery-related pins. The current datasheet says to connect unused QSTRT to ground. This is exactly why the generated project should be treated as a reviewable starting point, not a production reference: a named component and plausible topology make the mistake visible early enough to fix.

Common MAX17048 Schematic Mistakes

• Using the 8-bit address byte 0x6C where a driver expects the 7-bit address 0x36.
• Treating the MAX17048 as a charger, protection IC, or load switch instead of a fuel gauge.
• Copying a MAX17049 two-cell connection and assuming CELL is the MAX17048 voltage-sense input.
• Leaving QSTRT floating or tying it high when hardware quick-start is not required.
• Connecting ALRT to an MCU without a pull-up, a compatible voltage domain, or a firmware clear sequence.
• Adding pull-ups to every I2C board until the parallel resistance becomes too low.
• Powering the gauge from a switched system rail instead of confirming the required relationship to the cell.
• Placing the 0.1 µF bypass far from the WLP or routing its ground through charger and converter current paths.
• Reading only one byte of a two-byte register or applying the wrong byte order and scaling.
• Assuming the default battery model, room-temperature behavior, and a slow discharge test prove user-visible accuracy.
• Using a generic CSP footprint without checking the official WLP bump-side view, orientation mark, pad size, solder mask, and assembly process.

What SpeedUp Generates Before Engineering Review

SpeedUp can turn a product brief into a structured electronics architecture and editable KiCad sheets, so the MAX17048 is reviewed inside the actual charger, regulator, MCU, sensor, connector, and sleep-state context. A useful prompt should name the cell chemistry and capacity, charger input, peak load, standby target, desired battery-percentage behavior, MCU voltage, I2C devices, alert behavior, ship mode, enclosure limits, and preferred package.

The engineer still owns the manufacturer-document review, battery safety, component calculations, battery characterization, firmware, footprint approval, PCB layout, thermal behavior, sourcing, manufacturing, and validation. The value of the generated first schematic draft is that concrete pins, nets, footprints, and assumptions are available for review before they become expensive layout changes. The AI-generated KiCad schematic review guide shows how to apply the same discipline across the rest of a product.

Product boundary: For a MAX17048 battery product, SpeedUp can place the gauge inside the charger, regulator, MCU, I2C, alert, and operating-state architecture and produce structured sheets with an editable KiCad first draft. It does not characterize the battery, validate state-of-charge accuracy, approve battery safety, complete firmware, verify footprints and layout, or perform thermal, sourcing, compliance, and production validation. See the SpeedUp AI schematic generator workflow for the complete product-brief-to-editable-project path.

Related Battery and Schematic Resources

• Magnetic AI microphone KiCad project — the full battery-powered recorder example used in this guide.
• Battery-powered sensor circuit design checklist — power states, charging, regulation, sensing, and runtime decisions around the fuel gauge.
• I2C pull-up resistor value calculation — calculate the shared bus instead of copying one resistor value.
• KiCad schematic generator workflow — move from a product prompt to editable engineering artifacts.

FAQ

What is the MAX17048 I2C address?

The fixed 7-bit I2C address is 0x36. The write and read address bytes are 0x6C and 0x6D after the read/write bit is included. Check which form your MCU driver expects.

Does the MAX17048 need a current-sense resistor?

No. ModelGauge estimates state of charge without a current-sense resistor. The minimal circuit still needs the correct battery, supply, ground, 0.1 µF bypass, I2C pull-ups, and deliberate ALRT and QSTRT connections.

What is the difference between MAX17048 and MAX17049?

MAX17048 is intended for one cell, while MAX17049 is intended for two series cells. Their supply and voltage-sense connections differ, so do not reuse the MAX17049 CELL topology in a MAX17048 design without checking the exact datasheet application circuit.

Should MAX17048 QSTRT be pulled high?

No. Connect QSTRT to ground when hardware quick-start is unused. A deliberate rising edge can initiate quick-start, but firmware and the battery state must satisfy the manufacturer’s conditions before using it.

Can MAX17048 measure battery percentage while charging?

It continuously reports state of charge and rate across charging and discharging conditions, but accuracy still depends on the battery model, temperature compensation, cell behavior, system load, empty-voltage definition, and correct circuit implementation.