Tag: I2C

Quick Answer

SpeedUp turns product requirements for an MCP2221A USB-to-I2C/UART bridge into an electronics architecture for USB protection, power, reset, clocking, and serial interfaces, structured schematic sheets, and an editable KiCad project for engineering review. Explore the SpeedUp Demo: 100W Desktop Charging Station to see this handoff in a real project.

A reliable MCP2221A schematic starts with the power mode. For a 5 V USB-bus-powered circuit, connect VDD to the 5 V source and bypass VUSB locally with a 0.22 to 0.47 µF ceramic capacitor; remember that the UART and GPIO logic-high levels then follow the 5 V VDD rail. For a 3.3 V design, connect both VDD and VUSB to the regulated 3.3 V rail so the USB transceiver and external logic use the intended voltage.

Route USB D+ and D− as a controlled pair and add connector-level protection appropriate to the product, but do not automatically copy external USB series resistors: the current Microchip MCP2221A datasheet states that impedance matching is built in and no external resistors, capacitors, or magnetic components are necessary in the signal paths between the device and cable. Cross UTx to the target’s RX and URx to its TX, provide system-appropriate pull-ups on SDA and SCL, and confirm that the MCP2221A is the I2C host rather than a target. Finally, verify reset, GP startup functions, USB descriptors, package mapping, and the unusual QFN exposed-pad instruction before PCB layout.

What the MCP2221A Actually Provides

The MCP2221A is a USB 2.0 full-speed bridge that combines two different host-side interfaces in one device. It enumerates as a composite USB device: a Communication Device Class interface provides the virtual COM port for USB-to-UART traffic, while a Human Interface Device interface controls I2C, GPIO, configuration, ADC, DAC, clock output, and related functions. That distinction matters because “USB bridge” does not mean one transparent channel handles everything.

Function	MCP2221A behavior	Schematic implication
USB	Full-speed USB at 12 Mb/s; composite CDC and HID device	Plan enumeration, descriptors, USB power attributes, suspend behavior, connector protection, and the data pair
UART	UTx and URx only; 300 to 460800 baud; 8 data bits, no parity, one stop bit	Cross TX/RX, match the target voltage, and do not expect hardware RTS/CTS pins
I2C	I2C host up to 400 kHz; transactions arrive from the PC through USB HID	Add bus pull-ups and connect target devices; do not design the MCP2221A as an I2C target for an MCU
GP pins	Four multiplexed pins for GPIO and alternate functions	Define each startup function, direction, default output, and ownership before attaching target controls
Power	3.0 V to 5.5 V operating range; bus-powered or self-powered	Select the power mode first because VDD sets UART and GPIO voltage levels

The MCP2221A is accessed and configured from the USB side. The UART is a data path to another device; it is not a management port for the bridge itself. Likewise, the I2C block is a host that initiates transactions requested by the USB host. These ownership rules should appear in the block diagram and interface table before the detailed circuit is drawn.

MCP2221A Core Schematic Checklist

Review area	Pass condition	Common failure
Power mode	The drawing explicitly implements either 5 V bus power or 3.3 V self power	Mixing a 3.3 V VDD with a floating or capacitor-only VUSB connection
Logic voltage	UART, GPIO, I2C pull-ups, and target pins are compatible with VDD	Connecting 5 V UTx directly to a 3.3 V-only MCU input
USB data	D+/D− polarity, pair routing, ESD placement, return path, and connector mapping are reviewed	Copying unnecessary series parts or swapping the pair
UART	MCP2221A UTx reaches target RX; URx receives target TX	TX-to-TX labeling or ambiguous “RX” net names
I2C	The bridge is the host; pull-up rail and effective resistance are calculated for the entire bus	Missing pull-ups, duplicate strong pull-ups, or trying to address the bridge as a target
Reset and GP pins	Reset behavior and every GP startup function are documented	Leaving attached target controls in an unsafe state during USB enumeration
Package	Exact orderable package, symbol, pin numbers, NC pins, and footprint agree	Grounding the QFN exposed pad even though Microchip says not to connect it electrically
Configuration	USB VID/PID, strings, current request, self-powered attribute, and GP settings have owners	Treating factory defaults as a product configuration plan

Choose the Power Mode Before Wiring VUSB

VUSB powers the internal USB transceiver. It is not simply another name for the external USB connector’s VBUS pin, and its required connection changes with the chosen power architecture. Draw the rail names and source explicitly so a reviewer can tell which mode is intended without inferring it from capacitor values.

Power option	Required connection	External-interface consequence
5 V USB bus powered	Power VDD from USB 5 V and place a 0.22 to 0.47 µF ceramic bypass capacitor at VUSB	UART and GPIO logic highs follow the 5 V VDD domain; add translation or choose another mode for 3.3 V-only targets
3.3 V self powered	Tie both VDD and VUSB to the regulated 3.3 V rail	UART and GPIO logic levels align with 3.3 V targets; verify how USB attachment and the external rail interact in every power state
Product-specific hybrid	Use the manufacturer’s power-option guidance and make backfeed, sequencing, attach detection, and USB power attributes explicit	Do not connect two supplies together through the device or advertise the wrong bus-power behavior

Add a local VDD bypass capacitor and keep both power returns short. Microchip’s current USB-C breakout board uses 0.1 µF local capacitors and a 0.47 µF VUSB capacitor; its schematic is available in the official MCP2221A USB-C Breakout Board User Guide. Treat those values as a verified reference implementation, then check them against the exact power mode and board conditions.

If USB 5 V powers more than the bridge, calculate the connector load and inrush path. The MCP2221A datasheet notes that effective capacitance directly across VBUS and ground must remain within the USB limit unless inrush limiting is provided. Also review suspend current and decide whether the rest of the target board remains powered when the USB host suspends or disconnects.

Design the USB-C and D+/D− Path as One Interface

For a USB-C receptacle used as a USB 2.0 device, the connector needs the correct CC pulldowns, VBUS handling, shield strategy, ESD protection, and paired USB data connections. The MCP2221A does not negotiate USB Power Delivery. If the connector is used only for default USB device power and data, document that limitation and make sure the rest of the product does not depend on an unadvertised higher current.

The MCP2221A integrates the full-speed USB pull-up, termination behavior, and oscillator. Its datasheet specifically states that D+ and D− already contain impedance-matching resistors. That makes an automatic 22 Ω or 27 Ω “USB resistor” copied from another MCU a review item rather than a default requirement. Optional footprints may be useful during an unusual signal-integrity investigation, but the released schematic should explain why they exist and whether they are fitted or bypassed.

External ESD protection is a separate product-level choice. Select a low-capacitance device suitable for USB full-speed, place it close to the connector, and give surge current a short return path that does not cross the protected side. Then review the connector pin map, D+/D− polarity, stubs, pair spacing, ground continuity, shield bonding, and stack-up. The USB-C schematic checklist before PCB layout covers those connector and layout decisions in detail.

Wire UART for Direction, Voltage, and Bring-Up

Connect MCP2221A UTx to the target receiver and URx to the target transmitter. Net labels should describe the driver or full path—such as BRIDGE_TX_TO_TARGET_RX—instead of using a bare TX or RX name whose viewpoint changes between sheets. This one naming choice prevents a surprisingly common bring-up failure.

Voltage compatibility comes before baud rate. When VDD is 5 V, the MCP2221A UART and GPIO output highs are around the 5 V domain. A target powered from 3.3 V may not be 5 V tolerant. Powering both VDD and VUSB from 3.3 V is often the cleaner option for a 3.3 V embedded target, provided the entire USB power architecture is valid. Otherwise add appropriate translation and check direction, power-off behavior, leakage, and default states.

The UART exposes only UTx and URx; there are no dedicated RTS or CTS pins. The supported framing is 8-N-1, while the baud rate can range from 300 to 460800. If the target bootloader requires flow control, auto-reset, boot-strapping, or a break signal, assign GP pins deliberately or provide a separate reviewed circuit. Series resistors on the target UART can aid isolation or debugging, but their values and purpose should be documented rather than copied mechanically.

Treat MCP2221A I2C as a Host Bus

The MCP2221A initiates I2C transactions requested by the PC through USB HID. It supports host operation up to 400 kHz and can address normal 7-bit devices; Microchip’s host library also supports 10-bit addressing. It is not an I2C target that an embedded controller can discover and command. If the product needs an MCU to control the bridge locally, revisit the architecture instead of expecting the UART or I2C pins to provide a configuration back door.

SDA and SCL need pull-ups to a rail compatible with every device on the bus. Microchip’s current USB-C breakout board uses removable 2.2 kΩ pull-ups, but that does not make 2.2 kΩ universal. Calculate the effective parallel resistance, rise-time requirement, bus capacitance, sink current, cable or header length, and powered-off leakage for the actual system. The I2C pull-up resistor value guide provides the full calculation method.

For a debug adapter that connects to many unknown targets, consider making the pull-ups selectable or removable. Record which board owns them, expose a ground reference next to the bus, and prevent a host adapter from back-powering an unpowered target through SDA or SCL. Firmware or PC software should also have a recovery plan for a target that holds SDA low after an interrupted transaction.

Define Reset, GP Pins, and USB Configuration

The active-low reset input has an internal pull-up. An external pull-up, reset button, test point, or RC network can still be appropriate, but each part needs a reason and must respect the reset timing. Do not confuse the MCP2221A reset with the target MCU reset. If a GP pin controls the target reset or boot strap, show both signals separately and document the intended USB-host sequence.

The four GP pins are multiplexed. Depending on the pin, alternate functions include suspend status, UART activity LEDs, USB-configured status, clock output, ADC, DAC, and interrupt detection. Factory-default functions may drive or sample a pin before the PC application changes the runtime configuration. Any GP line attached to target reset, enable, boot mode, power control, or an LED should therefore be checked in power-up, reset, enumeration, suspend, disconnect, and application-controlled states.

The device stores USB and GP settings in internal Flash. Before shipping a product, define the VID/PID strategy, manufacturer and product strings, optional serial number, bus-powered versus self-powered attribute, requested USB current, remote-wakeup behavior, startup GP functions, output levels, and configuration protection. A development unit using Microchip defaults is not yet a product identity or provisioning process.

Verify the Exact Package and Footprint

The 14-pin through-hole and leaded packages use a straightforward one-through-fourteen pin map, while the 4 × 4 mm QFN rearranges the signals and adds two no-connect pins plus an exposed pad. Choose the orderable part before creating the symbol-footprint association. Check the top-view convention, pin-one mark, courtyard, land dimensions, solder-mask and paste rules, and the relationship between every signal name and physical pin.

Function	14-pin packages	QFN	Review note
VDD	1	16	Power source sets UART/GPIO levels
RST	4	3	Internal pull-up; document external reset circuit if present
URx / UTx	5 / 6	4 / 5	Cross to target TX/RX
SDA / SCL	9 / 10	8 / 9	I2C host bus; requires system pull-ups
VUSB	11	10	Connection depends on the power mode
D− / D+	12 / 13	11 / 12	Do not swap; integrated impedance matching
VSS	14	13	Provide a short ground return
NC / exposed pad	Not applicable	14, 15 / EP 17	Leave NC pins unconnected; Microchip says the exposed pad must not be electrically connected

Example From a Real SpeedUp MCP2221A KiCad Draft

The SpeedUp nRF54L15 development board project includes an MCP2221A-I/SL in its USB-C debug sheet. The generated subsystem gives the board a USB virtual COM path, a manual debug header, CC pulldowns, USB ESD protection, a reset pull-up, local capacitors, and isolated UART lines. It is useful evidence because the part appears inside a full development-board concept rather than as an isolated datasheet fragment.

Visible draft element	Useful intent	Required correction or confirmation
3.3 V rail on the MCP2221A VDD side	Targets 3.3 V UART compatibility	The visible VUSB pin appears connected only to a 0.47 µF capacitor; for 3.3 V operation, connect VUSB to 3.3 V as well and retain the required local bypassing
22 Ω resistors on D+ and D−	Shows that the USB data path was made reviewable	Current Microchip guidance says impedance matching is internal and external resistors are unnecessary; remove them or document a verified board-specific reason and fitting option
USBLC6-2SC6 protection near the data pair	Adds connector-level ESD intent	Confirm pin mapping, capacitance, protected-side orientation, physical placement, and a short surge return path
5.1 kΩ CC pulldowns	Represents a USB-C device connection	Verify both CC pins, connector footprint mapping, default-current assumptions, VBUS behavior, and whether the product needs anything beyond basic USB 2.0 device operation
100 Ω UART isolation resistors and named UART nets	Provides a separable target debug path	Confirm UTx-to-target-RX and URx-to-target-TX from pin numbers, not labels alone; verify voltage and signal quality
Unused I2C and GP pins	Keeps the minimal USB-UART use case simple	Mark unused functions intentionally and ensure no symbol pin or package pad has been misidentified

This review is the point of an editable first draft. A plausible component choice and organized sheet make the remaining decisions visible early: the VUSB rail, USB data components, target voltage, signal directions, connector exposure, and unowned pins can all be corrected before they become layout constraints. Use the broader AI-generated KiCad schematic review checklist to inspect the rest of the project with the same standard.

Common MCP2221A Schematic Mistakes

• Powering VDD at 3.3 V but leaving VUSB connected only to a capacitor instead of the 3.3 V rail.
• Powering VDD from 5 V and then connecting UTx or GP outputs directly to a 3.3 V-only target.
• Adding external USB series resistors because another MCU reference circuit used them, despite the MCP2221A’s built-in impedance matching.
• Swapping D+ and D− or relying on connector symbol labels without checking physical pad numbers.
• Connecting UTx to target TX and URx to target RX because both sheets use endpoint-relative net names.
• Expecting RTS/CTS hardware flow control when the device exposes only UTx and URx.
• Designing the MCP2221A as an I2C target instead of the host that initiates PC-requested transactions.
• Copying 2.2 kΩ or 4.7 kΩ pull-ups without calculating the complete bus and its parallel resistance.
• Ignoring factory GP assignments and allowing a startup alternate function to disturb target reset, enable, or boot pins.
• Grounding the QFN exposed pad even though the datasheet instructs designers not to connect it electrically.
• Leaving USB power attributes, requested current, descriptors, and provisioning until after hardware bring-up.

What SpeedUp Generates Before Engineering Review

SpeedUp can turn a product brief into a block diagram, component proposal, BOM context, and editable KiCad first schematic draft. For an MCP2221A interface, the prompt should state the USB connector, power source, target logic voltage, UART destination and baud-rate range, I2C devices and pull-up ownership, desired GP functions, debug header, protection requirements, and expected product power states.

The generated result still requires engineering review. Validate every power option, symbol pin, footprint, component value, USB rule, target voltage, interface direction, configuration assumption, layout constraint, and manufacturing decision against current primary documentation. The KiCad schematic generator workflow shows how to move from the product description to an editable handoff without treating the first output as production-ready.

Product boundary: For an MCP2221A bridge, SpeedUp can organize USB power, connector protection, UART, I2C, GPIO, target-voltage, and debug requirements into structured schematic sheets, BOM context, and an editable KiCad first draft. It does not verify USB compliance, target-side electrical safety, configuration behavior, firmware or host software, PCB routing, manufacturing test, or production readiness. See the SpeedUp AI schematic generator workflow for the complete product-brief-to-editable-project path.

FAQ

Does the MCP2221A need external USB series resistors?

No external impedance-matching resistors are required by the current datasheet. Microchip states that matching resistors are built into D+ and D− and that no external resistors, capacitors, or magnetic parts are necessary between the device and USB cable. External ESD protection and correct PCB routing remain separate design decisions.

Should MCP2221A VUSB connect to 3.3 V?

Yes, when the MCP2221A operates from a 3.3 V self-powered rail, both VDD and VUSB connect to 3.3 V. When VDD is powered at 5 V and the internal USB-transceiver regulator is used, VUSB instead requires a local 0.22 to 0.47 µF ceramic bypass capacitor.

Is the MCP2221A a USB-to-I2C target or host?

It is an I2C host. A PC application sends commands over USB HID, and the MCP2221A initiates the I2C transfers on SDA and SCL. It is not intended to appear as an addressable I2C target to another controller.

What UART voltage does the MCP2221A use?

The UART and GPIO voltage levels follow VDD. A 5 V VDD produces logic highs in the 5 V domain, while a 3.3 V VDD supports 3.3 V logic. Check the target’s input tolerance and output-high threshold before connecting the pins.

Does the MCP2221A need I2C pull-up resistors?

Yes. SDA and SCL need pull-ups provided by the bus design. The official Microchip USB-C breakout uses 2.2 kΩ removable pull-ups, but the correct value depends on the pull-up voltage, bus capacitance, speed, sink-current limit, cable or header length, and any other pull-ups already fitted.

Is an MCP2221A schematic generated by SpeedUp production ready?

No. It is an editable first schematic draft for structured engineering review. The real example on this page exposes power and USB-series-component questions that must be corrected or confirmed before layout, testing, compliance work, or manufacturing release.

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